This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.
☆37Oct 4, 2022Updated 3 years ago
Alternatives and similar repositories for arithmetic-encoder-av1
Users that are interested in arithmetic-encoder-av1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32May 18, 2019Updated 7 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A small badge showing a schematic of an mRNA vaccine nanoparticle and blinking the RNA sequence of the Moderna or Pfizer vaccines.☆44Aug 16, 2021Updated 4 years ago
- ☆13Jun 20, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Working on a Performance Analyser using ImGui☆12Aug 31, 2017Updated 8 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- ☆16Mar 2, 2021Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Example code for Padauk Microcontrollers.☆30Nov 17, 2022Updated 3 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆17Apr 17, 2021Updated 5 years ago
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆82Mar 14, 2026Updated 3 months ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 11 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆15Jan 15, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- A Synthesizable implementation of H.264 Video Decoding☆41Mar 2, 2016Updated 10 years ago
- CASLab-GPU simulator in SystemC☆11May 29, 2020Updated 6 years ago
- MBLANC: mini Board Lab and Companion☆11Jan 5, 2023Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 5 years ago
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 3 years ago
- Code for blog post "{n} times faster than C, where n = 128"☆11Jul 20, 2023Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆16Jan 25, 2026Updated 5 months ago
- ☆15Jul 14, 2024Updated last year
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆25Jan 27, 2023Updated 3 years ago
- Paper list for accleration of transformers☆14Jul 1, 2023Updated 3 years ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆22Jul 22, 2024Updated last year
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago