This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.
☆38Oct 4, 2022Updated 3 years ago
Alternatives and similar repositories for arithmetic-encoder-av1
Users that are interested in arithmetic-encoder-av1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32May 18, 2019Updated 7 years ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 6 months ago
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 4 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆26Feb 16, 2024Updated 2 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- Source code for 'Beginning Arduino' by Michael McRoberts☆10Mar 28, 2017Updated 9 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆31Aug 16, 2021Updated 5 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Working on a Performance Analyser using ImGui☆12Aug 31, 2017Updated 8 years ago
- [FCCM 2025] Code Samples for InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs☆15Mar 26, 2025Updated last year
- ☆16Mar 2, 2021Updated 5 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆83Mar 14, 2026Updated 5 months ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆67Apr 4, 2022Updated 4 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆19Apr 17, 2021Updated 5 years ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆93Apr 8, 2024Updated 2 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆15Jan 15, 2024Updated 2 years ago
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- Open Source Cell Library for Predictive CNFET Technology☆15Mar 12, 2026Updated 5 months ago
- Hardware-based VMAF☆11Aug 29, 2025Updated 11 months ago
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 12 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆16Jan 25, 2026Updated 6 months ago
- Implementation of BPSK QPSK ASK and FSK☆16Aug 7, 2020Updated 6 years ago
- AMC: Asynchronous Memory Compiler☆56Jun 29, 2020Updated 6 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 12 years ago
- Token ring communication protocol for low-cost, low-power embedded devices communicating over UART☆15May 3, 2018Updated 8 years ago
- ☆47Aug 23, 2023Updated 2 years ago