Note repository for studying Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL).
☆15Feb 17, 2025Updated last year
Alternatives and similar repositories for PCIe-CXL
Users that are interested in PCIe-CXL are comparing it to the libraries listed below
Sorting:
- Exploring CXL on QEMU Emulation☆36Mar 4, 2025Updated last year
- CXL Management Interface library☆24Jan 27, 2026Updated last month
- ☆115Jun 9, 2023Updated 2 years ago
- A curated list of open-source projects that help leverage CXL technology.☆26Sep 26, 2024Updated last year
- this is a repository based on gem5 and aims to be modified for CXL☆29Jul 29, 2023Updated 2 years ago
- A Gstreamer decryptor, with an implementation for OCDM.☆12Jun 7, 2022Updated 3 years ago
- Unofficial rockchip hareware video accelerate base on gstreamer gst-libav plugin☆12Oct 17, 2018Updated 7 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Oct 3, 2017Updated 8 years ago
- ☆13Nov 29, 2025Updated 3 months ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- Flexible Open-source workBench fOr Side-channel analysis (FOBOS)☆14Nov 19, 2025Updated 3 months ago
- A standalone CXL-enabled system simulator.☆19Jan 10, 2026Updated last month
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- ☆10Jul 16, 2023Updated 2 years ago
- ☆11Jan 22, 2021Updated 5 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12May 29, 2021Updated 4 years ago
- ☆26Feb 12, 2026Updated 3 weeks ago
- The development tree for OpenOCD for the Synopsys DesignWare ARC processor family☆15Aug 18, 2023Updated 2 years ago
- The official repository for the gem5 computer-system architecture simulator.☆14May 16, 2025Updated 9 months ago
- Black Duck Detect plugin for Jenkins☆12Nov 25, 2025Updated 3 months ago
- Port of the miscellaneous V4L2 tools for QNX 6.5 and above (mainly for devu-uvc project).☆12Mar 26, 2014Updated 11 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 3 years ago
- Contains all labs for EECS 251B for spring 2022☆12Mar 31, 2022Updated 3 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 4 years ago
- ☆16Mar 18, 2025Updated 11 months ago
- QEMU port for ARCv2 Processors☆15Oct 11, 2025Updated 4 months ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 11 years ago
- ☆16Oct 28, 2022Updated 3 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- codec2-android☆18May 12, 2014Updated 11 years ago
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆65Oct 18, 2025Updated 4 months ago
- Use hardware performance counters to find mapping of addresses to L3 slices in Intel processors☆17Jul 30, 2023Updated 2 years ago
- ☆14Mar 8, 2023Updated 3 years ago
- https://nvmexplorer.seas.harvard.edu NVMExplorer is a cross-stack design space exploration framework for evaluating and comparing on-chip…☆21Jun 21, 2024Updated last year
- Gem5 with PCI Express integrated.☆23Sep 29, 2018Updated 7 years ago
- ☆26Updated this week
- Universal USB video class driver for QNX 6.5 and above with V4L2 interface☆20Apr 26, 2016Updated 9 years ago