synogate / gatery
Gatery, a library for circuit design.
☆19Updated 2 months ago
Alternatives and similar repositories for gatery:
Users that are interested in gatery are comparing it to the libraries listed below
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated this week
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆29Updated this week
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- The multi-core cluster of a PULP system.☆69Updated this week
- Fiber-based SystemVerilog Simulator.☆25Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 7 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- A SystemVerilog source file pickler.☆54Updated 3 months ago
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆63Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆12Updated 4 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- IRSIM switch-level simulator for digital circuits☆31Updated 9 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆25Updated 4 years ago
- The specification for the FIRRTL language☆51Updated this week
- ☆32Updated this week
- FPGA Assembly (FASM) Parser and Generator☆90Updated 2 years ago
- ☆54Updated 2 years ago
- Simple runtime for Pulp platforms☆40Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆38Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 9 months ago
- Hardware generator debugger☆73Updated last year
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆58Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated last week
- A place to share libraries and utilities that don't belong in the core bsc repo☆33Updated 3 weeks ago
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- Logic circuit analysis and optimization☆31Updated 3 months ago
- Dual-issue RV64IM processor for fun & learning☆57Updated last year