Alternatives and similar repositories for gatery

Users that are interested in gatery are comparing it to the libraries listed below

• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆29Updated 3 weeks ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆105Updated 2 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 2 months ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆14Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• nbdd0121 / muntjac-soc
  SoC for muntjac
  ☆12Updated 4 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆37Updated 2 months ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 7 months ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated last month
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 7 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆148Updated last week
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated this week
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 5 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 10 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆86Updated 10 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago