Gatery, a library for circuit design.
☆27Jul 24, 2026Updated 3 weeks ago
Alternatives and similar repositories for gatery
Users that are interested in gatery are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆13Oct 20, 2021Updated 4 years ago
- This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin☆20Aug 8, 2022Updated 4 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- Amateur Radio Callsign RegEx Generator☆15Jul 12, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Automatic upload of ADIF log to CloudLog☆14Mar 10, 2025Updated last year
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 10 years ago
- ☆19Aug 30, 2020Updated 5 years ago
- Cross EDA Abstraction and Automation☆42Updated this week
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆18Jul 30, 2026Updated 2 weeks ago
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 5 years ago
- Reticle evaluation (PLDI 2021)☆12Apr 12, 2021Updated 5 years ago
- OpenHT FPGA design☆38Jun 24, 2024Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- high abstraction synthesis☆13Apr 8, 2024Updated 2 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆29Jul 7, 2026Updated last month
- ☆16May 7, 2025Updated last year
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 3 years ago
- BECE_Notes 📚 A comprehensive collection of organized study materials for Bachelor in Computer Engineering at Pokhara University. Contain…☆21Updated this week
- Experimental flows using nextpnr for Xilinx devices☆70Updated this week
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Updated this week
- a collection of antenna related designs (mostly based on the UniBalun Project)☆15Nov 7, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework☆97Updated this week
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆65Mar 12, 2026Updated 5 months ago
- A Python to VHDL compiler☆17Apr 28, 2025Updated last year
- .NET Core console app to push wsjtx_log.adi into Cloudlog☆22Feb 16, 2023Updated 3 years ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Jan 30, 2025Updated last year
- Fork of github.com/UCSBarchlab/OpenTPU for the TGPTPU project☆15Jun 1, 2025Updated last year
- Streaming FPGA/ASIC code generator for Google Protocol Buffers.☆19Jan 29, 2021Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Blazingly fast, modern C++ API using coroutines for efficient RTL verification and co-simulation via the VPI interface☆17Updated this week
- This shows a simple ARM bare-metal software implementation for gem5☆20Sep 26, 2021Updated 4 years ago
- Collection of Raspberry Pi Pico board adapters for use with Pico-DirtyJTAG☆15Jun 5, 2024Updated 2 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- Elements Software Development Kit☆13Jan 8, 2026Updated 7 months ago
- ☆12May 21, 2024Updated 2 years ago
- ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)☆58Jan 23, 2025Updated last year