Alternatives and similar repositories for Linux-Digilent-Dev:

Users that are interested in Linux-Digilent-Dev are comparing it to the libraries listed below

• DigilentInc / u-boot-Digilent-Dev
  The official Xilinx u-boot repository
  ☆7Updated 6 years ago
• DigilentInc / vivado-library
  ☆35Updated 6 years ago
• Digilent / linux-digilent
  Linux Repository for digilent boards
  ☆84Updated last month
• Digilent / ZYBO
  ☆61Updated 7 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆125Updated 4 years ago
• myriadrf / LimeSDR-PCIe_GW
  Altera Cyclone IV FPGA project for the PCIe LimeSDR board
  ☆37Updated 2 years ago
• Digilent / linux-Digilent-Dev
  Linux Kernel Repository for Digilent FPGA Boards (downstream from Xilinx Official Repository)
  ☆22Updated 8 years ago
• laurivosandi / hdl
  Collection of hardware description languages writings and code snippets
  ☆27Updated 9 years ago
• Avnet / hdl
  ☆107Updated last month
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆54Updated last month
• pabennett / uart
  A VHDL UART for communicating over a serial link with an FPGA
  ☆73Updated 8 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆88Updated 6 years ago
• Digilent / digilent-apps
  ☆14Updated last year
• LariSan / Digilent-Maker
  Code that goes with the Digilent Maker Space projects- to share and improve all code here is shared under the Creative Commons 3.0 Licens…
  ☆20Updated 10 years ago
• andrewsil1 / NexysPsram
  AXI PSRAM Controller IP for use with Digilent Nexys 4
  ☆10Updated 2 years ago
• OpenDGPS / zynq-axi-dma-sg
  Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
  ☆53Updated 7 years ago
• Digilent / u-boot-digilent
  u-boot-xarm from xilinx git repo with Digilent additions
  ☆31Updated 5 months ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆31Updated 9 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 7 years ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆188Updated 6 years ago
• f32c / arduino
  FPGArduino source
  ☆69Updated 5 years ago
• Architech-Silica / Zynq-Zedboard-Vivado-Workshop
  Zynq Workshop for Beginners
  ☆28Updated 9 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆173Updated 2 years ago
• myriadrf / LimeSDR-USB_GW
  Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board
  ☆100Updated 3 years ago
• AnttiLukats / OZOM-Model-A
  Open Hardware Zynq System on Module
  ☆29Updated 9 years ago
• Digilent / Petalinux-Zybo
  ☆26Updated 6 years ago