DigilentInc / Linux-Digilent-Dev
Fork of Xilinx's Linux repo that adds support for Digilent boards
☆10Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for Linux-Digilent-Dev
- The official Xilinx u-boot repository☆7Updated 6 years ago
- Open Source ZYNQ Board☆30Updated 9 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆36Updated 2 years ago
- ☆35Updated 6 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆53Updated this week
- Linux Repository for digilent boards☆85Updated 3 months ago
- u-boot-xarm from xilinx git repo with Digilent additions☆31Updated 3 months ago
- Zephyr port to riscv architecture☆24Updated 7 years ago
- Sample minimal Vivado project for Parallella FPGA☆43Updated 8 years ago
- Freecores website☆19Updated 7 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆52Updated 7 years ago
- Collection of hardware description languages writings and code snippets☆27Updated 9 years ago
- This is the base code using by the Mojo V3 to load the FPGA and act as a USB to serial port/ADC for the FPGA. This code is intended to be…☆35Updated 5 years ago
- AXI PSRAM Controller IP for use with Digilent Nexys 4☆10Updated 2 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆88Updated 6 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Updated 3 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆42Updated 8 years ago
- FPGArduino source☆69Updated 5 years ago
- It is a GPIO interrupt example for xilinx ZYNQ FPGA.☆13Updated 10 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- ZPUino HDL implementation☆89Updated 6 years ago
- OpenRISC Tutorials☆40Updated 3 months ago
- ☆61Updated 7 years ago
- Yet another free 8051 FPGA core☆29Updated 6 years ago
- LIB:Library for interacting with an FPGA over USB☆82Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- Wishbone <-> AXI converters☆13Updated 9 years ago
- ☆34Updated 7 years ago