Alternatives and similar repositories for CPU:

Users that are interested in CPU are comparing it to the libraries listed below

• zhangly / azpr_cpu
  用Altera FPGA芯片自制CPU
  ☆41Updated 10 years ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆111Updated 4 years ago
• lingscale / cc01
  ☆31Updated last month
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆143Updated 6 years ago
• oscourse-tsinghua / undergraduate-zwpu2019
  http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019
  ☆11Updated 5 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• rgwan / kamikaze
  Light-weight RISC-V RV32IMC microcontroller core.
  ☆104Updated 8 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆105Updated 2 years ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆312Updated last year
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆125Updated 5 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆69Updated 3 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 5 months ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆172Updated 3 years ago
• ilg-archived / riscv-none-gcc
  The GNU MCU Eclipse RISC-V Embedded GCC
  ☆78Updated 5 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆73Updated 3 years ago
• verimake-team / SparkRoad-FPGA
  ☆14Updated 5 years ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆37Updated 3 years ago
• lrscy / RISC-V-Emulator
  简单的RISC-V指令模拟器，实现了绝大多非扩展指令的模拟工作。
  ☆22Updated 7 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• jerry-jho / pyriscv
  A RISCV Emulator written in Python
  ☆45Updated 2 years ago
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆58Updated last year
• lizhirui / K210-Linux0.11
  Linux0.11 with MMU for K210(RISC-V) Version
  ☆90Updated 5 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆15Updated 4 years ago
• plctlab / plct-qemu
  PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。
  ☆28Updated 9 months ago
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆59Updated last year
• LvNA-system / labeled-RISC-V
  ☆169Updated 3 years ago
• xfguo / riscv-openwrt
  Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.
  ☆54Updated 6 years ago
• Lichee-Pi / Tang_E203_Mini
  LicheeTang 蜂鸟E203 Core
  ☆194Updated 5 years ago