kenter / OpenCL-FPGA-examplesLinks
☆19Updated 6 years ago
Alternatives and similar repositories for OpenCL-FPGA-examples
Users that are interested in OpenCL-FPGA-examples are comparing it to the libraries listed below
Sorting:
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated 2 months ago
- Virtual Platform for NVDLA☆153Updated 7 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated 2 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Updated 6 years ago
- ☆82Updated 7 months ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆164Updated 3 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆37Updated 5 years ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆18Updated 4 years ago
- ☆85Updated last year
- ☆88Updated 2 years ago
- Learn NVDLA by SOMNIA☆43Updated 5 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆22Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆108Updated 2 years ago
- A DSL for Systolic Arrays☆81Updated 6 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- ☆19Updated 5 years ago
- ☆97Updated last year
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- An FPGA integration and acceleration of the popular FAISS framework for approximate similarity search☆24Updated 6 years ago
- ☆33Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆63Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆87Updated 2 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- ☆183Updated this week