kenter / OpenCL-FPGA-examples

Related projects: ⓘ

• fpga-opencl-benchmarks / rodinia_fpga
  Rodinia Benchmark Suite for OpenCL-based FPGAs
  ☆29Updated last year
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 3 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆20Updated 3 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆26Updated 4 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• hipacc / hipacc-fpga
  Fork of Hipacc generating code for Vivado HLS and Altera OpenCL
  ☆24Updated 5 years ago
• pulp-platform / hero-sdk
  ⛔ DEPRECATED ⛔ HERO Software Development Kit
  ☆20Updated 2 years ago
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆43Updated 5 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆62Updated 4 years ago
• StanfordAHA / Halide-to-Hardware
  ☆76Updated this week
• jingpu / Halide-HLS
  HLS branch of Halide
  ☆76Updated 6 years ago
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆18Updated 4 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆17Updated 8 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆84Updated last year
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• ISU-RCL / cvBench
  Benchmarking Analysis of Vision Kernels on Embedded CPU, GPU and FPGA
  ☆14Updated 5 years ago
• SFU-HiAccel / rodinia-hls
  FPGA version of Rodinia in HLS C/C++
  ☆32Updated 3 years ago
• nvdla / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆32Updated 4 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆39Updated 5 years ago
• microideax / T-DLA
  ☆15Updated 4 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated last month
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• andrewbartolo / accel-sim
  Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing
  ☆7Updated 5 years ago
• UCLA-VAST / soda
  Stencil with Optimized Dataflow Architecture
  ☆15Updated 6 months ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆45Updated 9 months ago
• spcl / FBLAS
  BLAS implementation for Intel FPGA
  ☆75Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆56Updated 2 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 6 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆47Updated 5 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆28Updated 3 years ago