Alternatives and similar repositories for CPU

Users that are interested in CPU are comparing it to the libraries listed below

• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆112Updated 4 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆203Updated 3 years ago
• RegiaYoung / RISC-V-CPU
  记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
  ☆13Updated 3 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆81Updated 5 years ago
• TCL606 / MipsPipeline
  Mips五级流水线CPU
  ☆40Updated 2 years ago
• luyufan498 / CPU_start_from_0
  从零开始设计一个CPU (Verilog)
  ☆57Updated 4 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆82Updated 7 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆33Updated last year
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆91Updated 2 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆127Updated 5 years ago
• wzp21142 / mips-cpu-and-microsystem
  基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instructi…
  ☆16Updated 4 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆145Updated 6 years ago
• yuankong11 / MIPS_CPU
  一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU
  ☆11Updated 5 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆128Updated 4 years ago
• JianmingS / MIPS-architecture-CPU-design-based-on-FPGA
  基于FPGA的MIPS架构的CPU设计
  ☆30Updated 9 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 11 months ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆39Updated 4 years ago
• WanQiyang / mips-cpu
  UCAS 2017秋 计算机体系结构实验 MIPS流水线CPU
  ☆9Updated 7 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆65Updated 3 years ago
• yueyang2000 / riscv-cpu
  RISC-V multi cycle CPU. Project of Computer Organization (THU 2020)
  ☆16Updated 2 years ago
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆74Updated 3 years ago
• Mionger / mp3-player
  MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)
  ☆17Updated 6 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆135Updated 11 months ago
• 1Allison / 8bit-RISC-CPU
  用verilog设计8位cpu
  ☆7Updated 5 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 7 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆28Updated 3 years ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 9 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆28Updated 2 years ago
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆17Updated 4 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago