ruanshihai / CPULinks
Verilog实现的简单五级流水线CPU,开发平台:Nexys3
☆40Updated 10 years ago
Alternatives and similar repositories for CPU
Users that are interested in CPU are comparing it to the libraries listed below
Sorting:
- 通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器☆207Updated 3 years ago
- FPGA实现各种小游戏,学习并快乐着☆75Updated 3 years ago
- 用Altera FPGA芯片自制CPU☆41Updated 11 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆84Updated 5 years ago
- 基于FPGA的MIPS架构的CPU设计☆30Updated 9 years ago
- 【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。☆115Updated 5 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆148Updated 6 years ago
- 基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instructi…☆16Updated 4 years ago
- 从零开始设计一个CPU (Verilog)☆58Updated 4 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆129Updated 5 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 8 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆93Updated 7 years ago
- A MIPS CPU implemented in Verilog☆68Updated 7 years ago
- Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image☆68Updated 11 years ago
- 计算机体系结构课程☆18Updated 6 years ago
- 使用verilog编写sdram控制器☆12Updated 6 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆174Updated 4 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆61Updated 6 years ago
- ☆222Updated 4 years ago
- Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).☆91Updated last year
- 计算机组成原理课程设计内容,设计一个兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水结构),并增加IO模块(人机 交互式),解决数据依赖问题☆10Updated 5 years ago
- 中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session☆32Updated 8 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆30Updated 4 years ago
- 软件无线电,使用FPGA进行正交解调。☆22Updated 6 years ago
- 基于Xilinx Zynq 嵌入式软硬件协同设计实战指南☆83Updated 9 years ago
- ☆18Updated 2 years ago
- ☆31Updated 5 months ago