ruanshihai / CPU

Related projects ⓘ

Alternatives and complementary repositories for CPU

• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆109Updated 4 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆64Updated 4 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆126Updated 4 years ago
• luyufan498 / CPU_start_from_0
  从零开始设计一个CPU (Verilog)
  ☆50Updated 3 years ago
• TCL606 / MipsPipeline
  Mips五级流水线CPU
  ☆31Updated last year
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆113Updated 4 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 4 months ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆133Updated 5 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆73Updated 6 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆24Updated 3 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆32Updated 8 months ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆35Updated 3 years ago
• WanQiyang / mips-cpu
  UCAS 2017秋 计算机体系结构实验 MIPS流水线CPU
  ☆8Updated 6 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆40Updated 4 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆121Updated 4 months ago
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆37Updated 4 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆84Updated 2 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆104Updated 5 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆30Updated 7 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆190Updated 2 years ago
• Mionger / mp3-player
  MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)
  ☆15Updated 5 years ago
• fox6666 / RISC_V-pipeline
  基于RISC_V32I指令集架构的五级流水CPU
  ☆14Updated 5 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆50Updated 6 years ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆49Updated 2 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆52Updated last year