SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter
☆14Mar 21, 2017Updated 9 years ago
Alternatives and similar repositories for weighted_round_robin
Users that are interested in weighted_round_robin are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆44May 22, 2020Updated 6 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.☆13Jul 24, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆27May 23, 2026Updated 5 months ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆30Jul 5, 2026Updated 3 months ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- Extended Roofline Model - LLVM source tree with additional libraries for the analysis of the dynamic execution in the interpreter☆17Jul 5, 2017Updated 9 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Generic FIFO implementation with optional FWFT☆65May 27, 2020Updated 6 years ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆30Nov 21, 2020Updated 5 years ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 4 years ago
- Building a simple oscilloscope using FPGA board and PCB.☆22Dec 30, 2020Updated 5 years ago
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆12Jan 8, 2021Updated 5 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆48Sep 6, 2026Updated last month
- SPIREG - SPI slave logic for register access☆11Nov 12, 2025Updated 11 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- This repo contains all the materials needed to perform the ADALM-Pluto SDR Hands-On event developed by the Spanish MATLAB Ambassadors☆14Jul 8, 2022Updated 4 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- SIPEED Tang MEGA 138K with FPGA GOWIN GW5AST-138 SOC (Embedded RISC-V AE350)☆12Mar 12, 2024Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- ☆15Oct 9, 2026Updated 2 weeks ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆22Jul 14, 2022Updated 4 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 9 years ago
- FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.☆19Apr 26, 2017Updated 9 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆19Oct 23, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆26Feb 26, 2024Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆19Sep 21, 2025Updated last year
- A deep dive into the interrupt handling mechanisms within the Linux kernel. Explore how different devices, from keyboards to Ethernet por…☆11Oct 15, 2023Updated 3 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 10 months ago
- Direct Access Memory for MPSoC☆13Updated this week
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 8 years ago