UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC24xx microcontroller specification.
☆16Dec 23, 2024Updated last year
Alternatives and similar repositories for APB-SPI-Controller-Verification
Users that are interested in APB-SPI-Controller-Verification are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆16Apr 7, 2018Updated 8 years ago
- wifi☆12Jun 13, 2017Updated 9 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆14Aug 21, 2023Updated 2 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆54Jul 4, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆22Apr 11, 2022Updated 4 years ago
- 为了学习UVM验证相关知识,需要动手尝试实际的项目。作为一个初学者,难以接触到实际的项目,于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中,挑选出一个简单的小设计,作为我的验证对象,并围绕它编写了UVM验证环境。☆27Oct 9, 2020Updated 5 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆50Jun 19, 2020Updated 6 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆39Nov 30, 2022Updated 3 years ago
- Built a test environment using UVM Methodology to verify APB Protocol.☆16Feb 6, 2019Updated 7 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆20Jun 24, 2021Updated 5 years ago
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆20Feb 14, 2023Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆202Jul 23, 2018Updated 8 years ago
- UVM Verification IP to uart2bus IP.☆25Mar 7, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is for uvm_tb_gen☆55Feb 13, 2025Updated last year
- ☆30May 11, 2021Updated 5 years ago
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 12 years ago
- CORE-V MCU UVM Environment and Test Bench☆27Jul 19, 2024Updated 2 years ago
- UVM examples and projects☆169Jun 28, 2025Updated last year
- ☆52Nov 3, 2023Updated 2 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆69Aug 9, 2020Updated 6 years ago
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 12 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆117Jul 2, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Updated this week
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆36Mar 13, 2025Updated last year
- Verification of an Asynchronous FIFO using UVM & SVA☆13Jun 26, 2025Updated last year
- AHB to APB Bridge VIP☆30Mar 4, 2019Updated 7 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆32Jun 1, 2022Updated 4 years ago
- ☆12May 31, 2016Updated 10 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆28Mar 26, 2020Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- Sample UVM code for axi ram dut☆39Dec 14, 2021Updated 4 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- A complete UVM verification testbench for FIFO☆14Mar 21, 2016Updated 10 years ago
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆22Feb 7, 2025Updated last year
- Miscellaneous components for bluespec☆11Nov 18, 2024Updated last year