Dongtata2020 / UVM_Verification_for_P2S_Data_Converter
为了学习UVM验证相关知识,需要动手尝试实际的项目。作为一个初学者,难以接触到实际的项目,于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中,挑选出一个简单的小设计,作为我的验证对象,并围绕它编写了UVM验证环境。
☆22Updated 4 years ago
Alternatives and similar repositories for UVM_Verification_for_P2S_Data_Converter:
Users that are interested in UVM_Verification_for_P2S_Data_Converter are comparing it to the libraries listed below
- 数字IC秋招项目、手撕代码☆33Updated 8 months ago
- 支持AXI总线协议的8k×8 SP SRAM☆24Updated 4 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- ARM中通过APB总线连接的UART模块☆60Updated 4 years ago
- IC Verification & SV Demo☆48Updated 3 years ago
- ☆18Updated 4 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆90Updated 7 years ago
- 数字IC验证案例(SV and UVM)☆26Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆47Updated 3 years ago
- UVM实战随书源码☆46Updated 5 years ago
- System on Chip verified with UVM/OSVVM/FV☆23Updated 3 weeks ago
- AHB to APB Bridge VIP☆28Updated 5 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆39Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆115Updated 3 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆26Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆19Updated 2 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆161Updated 6 years ago
- UVM AHB VIP☆78Updated last month
- my UVM training projects☆29Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆74Updated 3 years ago
- DDR3 function verification environment in UVM☆22Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆56Updated last year
- Sample UVM code for axi ram dut☆30Updated 3 years ago
- Verification IP for I2C protocol☆40Updated 3 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆8Updated 3 weeks ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 7 years ago