Alternatives and similar repositories for clou:

Users that are interested in clou are comparing it to the libraries listed below

• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆12Updated 4 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆15Updated last week
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆35Updated this week
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• CHERIoT-Platform / cheriot-sail
  Sail code model of the CHERIoT ISA
  ☆37Updated 3 weeks ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 5 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 6 years ago
• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 3 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆79Updated this week
• uw-unsat / serval-sosp19
  This repo contains the artifact for our SOSP'19 paper on Serval
  ☆30Updated 5 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆35Updated 2 years ago
• jiegec / apple-pmu
  Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS
  ☆12Updated last week
• CTSRD-CHERI / cheri-specification
  CHERI ISA Specification
  ☆24Updated 8 months ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆32Updated 3 years ago
• riscvarchive / riscv-code-speed-optimization
  ☆12Updated 4 years ago
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆58Updated last week
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆36Updated last week
• anishathalye / knox
  A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏
  ☆33Updated 2 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated this week
• ymanerka / rtlcheck
  RTLCheck
  ☆21Updated 6 years ago
• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆19Updated 3 weeks ago
• andreas-abel / XED-to-XML
  XML representation of the x86 instruction set
  ☆28Updated last week
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 4 months ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆38Updated 5 months ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆13Updated 2 years ago