nmosier / clou
☆10Updated last year
Alternatives and similar repositories for clou:
Users that are interested in clou are comparing it to the libraries listed below
- Sail code model of the CHERIoT ISA☆34Updated last month
- Iodine: Verifying Constant-Time Execution of Hardware☆12Updated 3 years ago
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- RISC-V BSV Specification☆18Updated 5 years ago
- ☆19Updated 10 years ago
- COATCheck☆13Updated 6 years ago
- Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready☆36Updated 3 years ago
- A tool to enable fuzzing for Spectre vulnerabilities☆30Updated 5 years ago
- QARMA block cipher in C☆26Updated 2 years ago
- Embedded Universal DSL: a good DSL for us, by us☆32Updated this week
- Code templates to get started experimenting with the RISC-V LLVM toolchain☆13Updated 6 years ago
- Testing processors with Random Instruction Generation☆32Updated 2 weeks ago
- The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…☆45Updated this week
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 7 months ago
- oo7, a binary analysis tool to defend against Spectre vulnerabilities☆32Updated 4 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆77Updated last week
- XML representation of the x86 instruction set☆28Updated 2 years ago
- QEMU with support for CHERI☆57Updated this week
- Code repository for Coppelia tool☆22Updated 4 years ago
- Decompose source code into templates and fragments for any language.☆21Updated 2 years ago
- CHERI C/C++ Programming Guide☆29Updated this week
- An LLVM based mini-C to Verilog High-level Synthesis tool☆35Updated last year
- A Tool for the Static Analysis of Cache Side Channels☆39Updated 7 years ago
- ☆9Updated 2 years ago
- A programming language to write bitsliced ciphers☆56Updated 5 months ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆20Updated 2 years ago
- Tool for inferring cache replacement policies with automata learning. Uses LearnLib and Sketch.☆16Updated 4 years ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆122Updated 5 months ago
- CHERI-RISC-V model written in Sail☆57Updated 2 weeks ago
- Some experiments with SMT solvers and GIMPLE IR☆36Updated last year