boltma / Scalable-FeFETLinks
☆17Updated 3 years ago
Alternatives and similar repositories for Scalable-FeFET
Users that are interested in Scalable-FeFET are comparing it to the libraries listed below
Sorting:
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆25Updated 3 months ago
- a Computing In Memory emULATOR framework☆14Updated last year
- ☆18Updated last year
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆75Updated 3 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 2 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆24Updated 4 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆29Updated 2 years ago
- Code of "Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures", TCAD 2020☆11Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆74Updated 9 months ago
- view at https://xupsh.github.io/ccc2021/☆23Updated 3 years ago
- Lightening-Transformer: A Dynamically-operated Optically-interconnected Photonic Transformer Accelerator, HPCA'24☆39Updated 10 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆74Updated last year
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆104Updated last month
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 3 weeks ago
- Verilog Implementation of 32-bit Floating Point Adder☆44Updated 5 years ago
- ☆10Updated last year
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 3 years ago
- ☆71Updated 7 years ago
- ☆31Updated 2 years ago
- ☆39Updated 6 years ago
- ☆46Updated last year
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated 2 years ago
- sram/rram/mram.. compiler☆43Updated 2 years ago
- Architecture for RRAM multilevel programming☆17Updated 7 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆68Updated 4 months ago
- ECE 5745 Tutorial 8: SRAM Generators☆15Updated 3 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago