balanx / vbppLinks
Verilog PreProcessor.
☆10Updated 9 years ago
Alternatives and similar repositories for vbpp
Users that are interested in vbpp are comparing it to the libraries listed below
Sorting:
- An HLS-synthesizable Dynamic Memory Manager for FPGAs☆10Updated 3 years ago
- Here is a bunch of util IPs☆9Updated 6 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆18Updated 7 months ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Updated 10 years ago
- Educational 16-bit MIPS Processor☆17Updated 6 years ago
- PulseRain FP51-1T MCU core☆9Updated 7 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Simple MIDAS Examples☆12Updated 6 years ago
- IP cores for the FPGA Libre project☆12Updated 7 years ago
- Enigma in FPGA☆29Updated 6 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- Simulation VCD waveform viewer, using old Motif UI☆26Updated 2 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 4 years ago
- Yosys Plugins☆21Updated 5 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Updated 4 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆28Updated 5 years ago
- WISHBONE Builder☆14Updated 8 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 10 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last month
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Wishbone controlled I2C controllers☆50Updated 7 months ago
- Wishbone <-> AXI converters☆14Updated 10 years ago
- Synthesiser for Asynchronous Verilog Language☆20Updated 10 years ago
- A Verilog Synthesis Regression Test☆37Updated last year