Alternatives and similar repositories for vbpp

Users that are interested in vbpp are comparing it to the libraries listed below

• diamantopoulos / memluv
  An HLS-synthesizable Dynamic Memory Manager for FPGAs
  ☆10Updated 3 years ago
• MorgothCreator / VerilogUtilIP
  Here is a bunch of util IPs
  ☆9Updated 6 years ago
• FISC-Project / FISC-VHDL
  FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
  ☆15Updated 5 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆40Updated 9 years ago
• onchipuis / mriscv_vivado
  A 32-bit Microcontroller for NEXYS4-DDR fpga based on mriscv.
  ☆13Updated 8 years ago
• ucb-bar / midas-examples
  Simple MIDAS Examples
  ☆12Updated 6 years ago
• stffrdhrn / uart
  Verilog uart receiver and transmitter modules for De0 Nano
  ☆18Updated 10 years ago
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 9 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated 7 months ago
• nakultirumalai / VLSIPlacement
  Code for new techniques of VLSI placement
  ☆13Updated 11 years ago
• mmicko / enigmaFPGA
  Enigma in FPGA
  ☆29Updated 6 years ago
• apertus-open-source-cinema / alpha-software
  Axiom Alpha prototype software (FPGA, Linux, etc.)
  ☆30Updated 9 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated 10 months ago
• FPGALibre / fpgacores
  IP cores for the FPGA Libre project
  ☆12Updated 7 years ago
• wsong83 / Asynchronous-Verilog-Synthesiser
  Synthesiser for Asynchronous Verilog Language
  ☆20Updated 10 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• AmiArnab / Synopsys
  Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler
  ☆10Updated 7 years ago
• JohnDMcMaster / xilinx-usb-driver
  Mirror of git://git.zerfleddert.de/usb-driver
  ☆20Updated 11 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• bluecmd / wb-axi
  Wishbone <-> AXI converters
  ☆14Updated 10 years ago
• freecores / mips_16
  Educational 16-bit MIPS Processor
  ☆17Updated 6 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆18Updated 8 months ago
• PulseRain / FP51_fast_core
  PulseRain FP51-1T MCU core
  ☆9Updated 8 years ago
• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated last month
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆22Updated 4 years ago
• freecores / mmuart
  Simple RS232 UART
  ☆12Updated 9 years ago
• stass / md5_core
  MD5 core in verilog
  ☆13Updated 13 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• ashleyjr / Verilog
  ☆10Updated 6 years ago