alastairreid / mra_tools
Tools to process ARM's Machine Readable Architecture Specification
☆128Updated 5 years ago
Alternatives and similar repositories for mra_tools
Users that are interested in mra_tools are comparing it to the libraries listed below
Sorting:
- Example implementation of Arm's Architecture Specification Language (ASL)☆116Updated 5 years ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆41Updated last week
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆79Updated last month
- rmem public repo☆41Updated last month
- Symbolic execution tool for Sail ISA specifications☆66Updated last month
- Semantics of x86-64 in K☆151Updated 5 years ago
- The Captive Hypervisor☆42Updated 2 years ago
- A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.☆347Updated 8 months ago
- Liveness-driven random C code generator☆41Updated 10 months ago
- A new context, field, and array-sensitive heap analysis for LLVM bitcode based on DSA.☆165Updated 11 months ago
- Automatic detection of speculative information flows☆68Updated 3 years ago
- Experimental translation of llvm to smt.☆56Updated 5 years ago
- ☆52Updated 9 years ago
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays a…☆249Updated last week
- DebugIR: Debugging LLVM-IR Files☆138Updated 5 months ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆126Updated 8 months ago
- Generates CIL MLIR dialect from C/C++ source.☆32Updated 4 years ago
- Source code for the equivalence checker presented in the PLDI 2019 paper, "Semantic Program Alignment for Equivalence Checking"☆42Updated 5 years ago
- Automatic inference of a formal specification of the x86_64 instruction set☆70Updated 9 years ago
- CCG is a random C Code Generator☆44Updated 2 years ago
- QEMU with support for CHERI☆58Updated 3 weeks ago
- RISC-V Instruction Set Metadata☆41Updated 6 years ago
- Verified, Incremental, Binary Editing with Synthesis☆54Updated 2 years ago
- Fork of LLVM adding CHERI support☆52Updated 3 weeks ago
- Assembly super-optimization via constraint solving☆188Updated this week
- Constraint solver based on coverage-guided fuzzing☆246Updated last year
- XML representation of the x86 instruction set☆28Updated last week
- Basic SAT model of x86 instructions using Z3, autogenerated from Intel docs☆317Updated 3 years ago
- Binary Translator to LLVM IR☆219Updated 2 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆67Updated this week