Alternatives and similar repositories for learn_prefetcher:

Users that are interested in learn_prefetcher are comparing it to the libraries listed below

• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆59Updated last year
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• cry-daniel / Computer-Architecture-Learning
  ☆59Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• miaochenlu / Gem5_tutorials
  ☆18Updated last year
• OpenXiangShan / GEM5
  ☆76Updated this week
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆33Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆28Updated 2 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated 2 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆13Updated 3 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• SamAinsworth / gem5-triangel
  ☆12Updated 3 weeks ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 6 months ago
• hanhwi / SimPoint
  ☆12Updated 2 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆24Updated 3 weeks ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 4 months ago
• JamesAslan / MicroArchBench
  ☆67Updated 5 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.
  ☆32Updated this week
• bakhshalipour / Bingo
  The source code of "Bingo Spatial Data Prefetcher" paper, which is accepted in HPCA 2019.
  ☆25Updated 3 years ago
• dhschall / LLBP
  Branch predictor simulation framework for the Last-Level Branch Predictor
  ☆21Updated 7 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 8 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆17Updated last month
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆13Updated 3 years ago