Alternatives and similar repositories for learn_prefetcher:

Users that are interested in learn_prefetcher are comparing it to the libraries listed below

• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆58Updated last year
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆33Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• SamAinsworth / gem5-triangel
  ☆12Updated 3 weeks ago
• OpenXiangShan / GEM5
  ☆74Updated this week
• miaochenlu / Gem5_tutorials
  ☆18Updated last year
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆27Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 5 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆58Updated 2 years ago
• OSCPU / chisel-playground
  ☆60Updated 3 weeks ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 3 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆35Updated this week
• mytbk / gem5-docs
  gem5 相关中文笔记
  ☆14Updated 3 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• topanitanw / Cacti-7.0
  ☆9Updated last month
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆17Updated last month
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 7 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆16Updated last week
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆13Updated 2 months ago
• sequencer / arithmetic
  ☆32Updated last week
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆20Updated 2 months ago
• hanhwi / SimPoint
  ☆11Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆28Updated 10 months ago