mediaic / VLSI_Lab2
RTL + Verfication + Synthesis + APR
☆10Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for VLSI_Lab2
- RTL + Synthesis + APR☆11Updated last year
- Deep Learning & VLSI Crash Course for New Members☆35Updated 3 months ago
- ☆29Updated last year
- SystemVerilog vim scripts☆65Updated last year
- IC Contest☆24Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 6 years ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆88Updated 2 months ago
- ☆10Updated 3 years ago
- biRISC-V - 32-bit dual issue RISC-V CPU Software Environment☆10Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆225Updated 6 months ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆168Updated last year
- Computer-Aided VLSI System Design☆16Updated 3 weeks ago
- ☆28Updated last year
- Novel GUI Based UVM Testbench Template Builder☆119Updated 3 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆297Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆177Updated this week
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆12Updated last year
- Network on Chip Simulator☆240Updated 10 months ago
- 第五小组☆8Updated 6 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆13Updated 9 months ago
- ☆19Updated this week
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆31Updated 3 weeks ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆93Updated 10 years ago
- Examples and reference for System Verilog Assertions☆82Updated 7 years ago
- ☆11Updated 3 years ago
- 紀錄一下自己寫過的所有Lab☆20Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆158Updated 2 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆110Updated 6 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆178Updated 7 years ago