hukenovs / mathLinks
Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
☆30Updated 5 years ago
Alternatives and similar repositories for math
Users that are interested in math are comparing it to the libraries listed below
Sorting:
- Audio Signal Processing SoC☆20Updated 7 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32Updated 8 years ago
- Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-s…☆21Updated 7 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆12Updated 5 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆67Updated last year
- A simple and crude CIC filter implementation in Python3 for learning purposes☆22Updated 6 years ago
- Verilog modules for software-defined radio.☆18Updated 13 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆127Updated 4 years ago
- VHDL Library for implementing common DSP functionality.☆31Updated 7 years ago
- VHDL Modules☆24Updated 10 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆61Updated 3 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- LiteX based FPGA gateware for Thunderscope.☆29Updated 3 weeks ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆30Updated 4 years ago
- 利用ZYNQ7020实现SAR数据采集系统,其中包含硬件设计代码、上位机、测试程序。☆13Updated 11 months ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆76Updated 5 years ago
- GSI Timing Gateware and Tools☆14Updated this week
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- My code repositry for common use.☆23Updated 4 years ago
- FPGA accelerator on GNU Radio and Zynq SoC☆16Updated 8 years ago
- MATLAB-based FIR filter design☆62Updated last year
- Time to Digital Converter (TDC)☆36Updated 5 years ago
- Fractional interpolation using a Farrow structure☆10Updated 2 years ago
- Projects published on controlpaths.com and hackster.io☆42Updated 3 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆112Updated 9 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Updated 10 years ago
- Audio controller (I2S, SPDIF, DAC)☆92Updated 6 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- IEEE 802.16 OFDM-based transceiver system☆28Updated 6 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago