roboticvedant / Verilog-PID-ControllerLinks
This repo features a Verilog-based PID controller optimized for real-time ASIC and FPGA applications. It includes a testbench for linear system validation and is under active development to integrate Model Predictive Control for enhanced robustness. Ideal for time-sensitive, high-precision tasks.
☆25Updated 2 years ago
Alternatives and similar repositories for Verilog-PID-Controller
Users that are interested in Verilog-PID-Controller are comparing it to the libraries listed below
Sorting:
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 5 years ago
- Repository for the development of an FPGA based DSP Lock-In Amplifier☆72Updated 2 years ago
- Open source AMD Xilinx Kria UltraScale+ SoM baseboard☆57Updated 10 months ago
- Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA☆72Updated 5 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆68Updated 4 years ago
- Repository for FPGA projects☆57Updated last week
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆22Updated 2 years ago
- A Python package to use FPGA development tools programmatically.☆143Updated 8 months ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆66Updated 10 years ago
- Course material for a basic hands-on analog circuit design course with IC emphasis☆167Updated this week
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆61Updated 3 months ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Updated 4 years ago
- Vitis Model Composer Examples and Tutorials☆112Updated last week
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Updated 10 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆36Updated 3 years ago
- A series of CORDIC related projects☆119Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆185Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆70Updated 5 years ago
- AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications☆41Updated 3 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆125Updated 4 years ago
- All digital PLL☆28Updated 7 years ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆70Updated 3 weeks ago
- ☆19Updated 2 years ago
- ☆30Updated 4 years ago
- Files for Advanced Integrated Circuits☆32Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- MIPI CSI-2 + MIPI CCS Demo☆74Updated 4 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago