tchoi8 / verilogView external linksLinks
learning VHDL
☆12Jul 1, 2014Updated 11 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below
Sorting:
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- All of my Verilog_HDL codes☆11Apr 5, 2021Updated 4 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- MICRO 2023 Evaluation Artifact for TeAAL☆10Oct 26, 2023Updated 2 years ago
- ☆20May 8, 2012Updated 13 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- A friendly UI for arXiv hosting papers on fairness and ethics in Machine Learning & Data Science☆12Jul 4, 2019Updated 6 years ago
- 8 labs of course Introduction to Computer System☆10Jun 17, 2014Updated 11 years ago
- ⚖️ Code for the paper "Ethical Adversaries: Towards Mitigating Unfairness with Adversarial Machine Learning".☆11Dec 8, 2022Updated 3 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- C++ utilities for lexing and parsing of script languages and configuration files.☆12Dec 23, 2017Updated 8 years ago
- Can Large Language Models Identify Authorship? (EMNLP 2024 Findings)☆12Feb 4, 2025Updated last year
- 2D platformer game where you play as a non-flying kind of duck.☆10Apr 9, 2018Updated 7 years ago
- ☆12Sep 8, 2017Updated 8 years ago
- A vscode extension for designing AIGC applications.☆11Jan 15, 2024Updated 2 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Apr 2, 2025Updated 10 months ago
- 使用javascript实现的类似yacc/bison的语法解析器的生成器☆17Nov 20, 2017Updated 8 years ago
- gdb pretty printer for llvm's libcxx☆11Mar 9, 2018Updated 7 years ago
- Adversarial learning by utilizing model interpretation☆10Oct 19, 2018Updated 7 years ago
- FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64☆15Aug 22, 2019Updated 6 years ago
- Neural Turing Machine☆13Jun 18, 2018Updated 7 years ago
- An easy-to-run implementation for finetuning large language models (LLMs) such as llama and gemma, supporting full parameter finetuning, …☆12May 6, 2024Updated last year
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 6 years ago
- Netlist and Verilog Haskell Package☆18Nov 21, 2010Updated 15 years ago
- Code for ICML 2022 paper: Achieving Fairness at No Utility Cost via Data Reweighing with Influence☆11Aug 3, 2022Updated 3 years ago
- mit-6.824-2012☆42Jun 28, 2015Updated 10 years ago
- ☆33Nov 14, 2025Updated 3 months ago
- High-performance key-value store☆12Dec 31, 2018Updated 7 years ago
- Java library for decoding Iridium Short Burst Data packets.☆10Jun 15, 2023Updated 2 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 5 years ago
- A simple sql parser with context-free grammer, predictive parser and lexer with DFA☆12Oct 29, 2015Updated 10 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆13Nov 28, 2019Updated 6 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 3 years ago
- ☆10Apr 16, 2021Updated 4 years ago
- Multi-thread version of simdjson☆15Jul 27, 2019Updated 6 years ago
- This repository provides a summarization of recent empirical studies/human studies that measure human understanding with machine explanat…☆14Jul 24, 2024Updated last year