learning VHDL
☆12Jul 1, 2014Updated 12 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A vscode extension for designing AIGC applications.☆12Jan 15, 2024Updated 2 years ago
- ☆16Mar 22, 2021Updated 5 years ago
- Collection of projects for adding GNURadio to a REDHAWK Domain as a Component, thus enabling easy installation of flowgraphs into REDHAWK…☆15Jul 15, 2019Updated 7 years ago
- All of my Verilog_HDL codes☆11Apr 5, 2021Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- GNURadio block to determine unkown symbol rates☆19Mar 25, 2022Updated 4 years ago
- Python/Qt4/GnuRadio suite for receiving satellites.☆14Apr 21, 2018Updated 8 years ago
- Replacement routine for discover_netsdr and other misc programs☆16Jul 6, 2025Updated last year
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆44Jun 6, 2021Updated 5 years ago
- Use FPGA to Transfer Image with Gigabits Ethernet☆19Dec 2, 2020Updated 5 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 7 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64☆15Aug 22, 2019Updated 6 years ago
- Netlist and Verilog Haskell Package☆19Nov 21, 2010Updated 15 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 6 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Traefikv2 reverse proxy plus Portainer Docker manager and Adminer DB manager, together with a cats demo app☆12Nov 7, 2021Updated 4 years ago
- Contains code of Python,c and c++☆12May 31, 2024Updated 2 years ago
- Open Infrastructure Manager (OIM) is an open source project which simplifies the integration of storage and network acceleration into clo…☆15Aug 4, 2022Updated 3 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- some old code about scheme compiler I've ever wrote☆14Jun 21, 2025Updated last year
- ☆18Sep 16, 2020Updated 5 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- A power-modulated jammer in GnuRadio☆23Jan 14, 2022Updated 4 years ago
- verilog tutorials for iCE40HX8K Breakout Board☆23Mar 2, 2016Updated 10 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- Implementation of different types of adder circuits☆16Jan 5, 2016Updated 10 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆114Oct 31, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- C++ utilities for lexing and parsing of script languages and configuration files.☆12Dec 23, 2017Updated 8 years ago
- Tutorial for creating new OOT modules for GNU Radio that leverage pyCUDA.☆25Jul 24, 2023Updated 2 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Regular expressions for humans, a port of Ruby's Regularity library to R (see https://github.com/kevinushey/rex for current development)☆20Sep 24, 2014Updated 11 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago