jaybee-117 / Verilog_CodesLinks
All of my Verilog_HDL codes
☆11Updated 4 years ago
Alternatives and similar repositories for Verilog_Codes
Users that are interested in Verilog_Codes are comparing it to the libraries listed below
Sorting:
- Solution to COA LAB Assgn, IIT Kharagpur☆36Updated 6 years ago
- This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum☆53Updated 3 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 7 months ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆42Updated 4 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆36Updated 6 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- Architectural design of data router in verilog☆31Updated 5 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆27Updated last year
- ☆16Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆11Updated 7 months ago
- All the projects and assignments done as part of VLSI course.☆19Updated 4 years ago
- ☆17Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- ☆17Updated last year
- An 8 input interrupt controller written in Verilog.☆27Updated 13 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆110Updated 3 years ago
- ☆22Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- ☆9Updated 2 years ago
- ☆10Updated last year
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆21Updated 9 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆49Updated 11 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated last year
- System Verilog using Functional Verification☆12Updated last year
- ☆10Updated last year
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- ☆41Updated last year