jaybee-117 / Verilog_Codes

Related projects: ⓘ

• vedic-partap / Computer-Organization-and-Architecture-LAB
  Solution to COA LAB Assgn, IIT Kharagpur
  ☆35Updated 5 years ago
• ashok-g-r / 100-Days-of-RTL
  ☆15Updated last year
• SinghCoder / Icarus_Verilog
  This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
  ☆41Updated 2 years ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆92Updated 2 years ago
• semiDESIgner / 50daysRTLcode
  ☆16Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆15Updated 11 months ago
• merledu / Google-Summer-of-Code
  Project ideas list for Google Summer of Code.
  ☆11Updated 7 months ago
• stevehoover / makerchip_examples
  ☆14Updated last week
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆26Updated 4 years ago
• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆23Updated 3 months ago
• Prananya123 / RTL-Coding
  ☆22Updated last year
• UtkarshPathrabe / Computer-Architecture-Lab-Solutions-BITS-Pilani
  Contains the Lab Sheets and their Solutions of the Computer Architecture Course in BITS Pilani
  ☆18Updated 8 months ago
• Prajwal-ECE / RTL-Coding
  ☆9Updated last year
• parasgidd / avsdpll_3v3
  This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…
  ☆15Updated 2 years ago
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆17Updated 3 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆29Updated last year
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆68Updated 10 months ago
• Akashtailor-exe / 30-days-of-verilog
  30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…
  ☆27Updated 11 months ago
• ashishrana160796 / verilog-starter-tutorials
  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
  ☆54Updated 3 years ago
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆24Updated 12 years ago
• Artityagi123456789 / 100DaysofRTL
  ☆13Updated 6 months ago
• IEEE-NITK / VLSI_design-of-RISC
  IEEE Executive project for the year 2021-2022
  ☆8Updated last year
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆12Updated 2 years ago
• karribharathi / 100-Days-of-RTL
  ☆16Updated 8 months ago
• mihir8181 / VerilogHDL-Codes
  Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
  ☆34Updated 5 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆49Updated last year
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆33Updated 2 years ago
• SudhakarKuma / IITB-Campus-Placement-Resumes
  Resumes of IITB students placed in 2020-21
  ☆58Updated 2 years ago
• deepvyas / Verilog-Snippets
  Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
  ☆17Updated 6 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆25Updated 2 years ago