k0nze / zedboard_pl_to_ps_interrupt_example

Related projects ⓘ

Alternatives and complementary repositories for zedboard_pl_to_ps_interrupt_example

• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆87Updated 4 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 2 years ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆140Updated 10 months ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆106Updated 3 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆30Updated last month
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆99Updated 10 months ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆40Updated 3 years ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆34Updated 3 years ago
• DiegoRosales / VHDL_Modules
  VHDL Modules
  ☆23Updated 9 years ago
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆30Updated 5 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆77Updated last year
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆93Updated last week
• oetr / FPGA-I2C-Minion
  A simple I2C minion in VHDL
  ☆60Updated 5 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆55Updated 2 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆41Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆28Updated 8 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆109Updated 10 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆108Updated this week
• farbius / dsp_xilinx_ip
  Some basic DSP algorithms implemented with xilinx IP cores with explanation, Verilog testbenches and modelling in Python
  ☆31Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆74Updated 2 years ago
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆38Updated 7 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆64Updated 7 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆56Updated 8 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆43Updated 11 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆99Updated this week
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• nandland / memory
  Single Port RAM, Dual Port RAM, FIFO
  ☆20Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year