Alternatives and similar repositories for device-modeling-language

Users that are interested in device-modeling-language are comparing it to the libraries listed below

• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆119Updated 5 months ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆46Updated last month
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆27Updated 2 years ago
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆79Updated 3 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 5 months ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated last week
• riscvarchive / riscv-code-size-reduction
  ☆148Updated last year
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆220Updated 3 months ago
• antmicro / rowhammer-tester
  ☆73Updated 3 weeks ago
• quic / qbox
  Qbox
  ☆83Updated last week
• riscv-admin / riscv-ovpsim
  ☆61Updated 5 years ago
• larkmjc / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆205Updated this week
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆52Updated 3 weeks ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 3 weeks ago
• riscv / riscv-aia
  ☆99Updated 3 weeks ago
• embench / embench-iot
  The main Embench repository
  ☆301Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆146Updated this week
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆57Updated this week
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆34Updated this week
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆108Updated 7 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆46Updated 4 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆110Updated 5 months ago
• luizinhosuraty / pciemu
  PCIe Device Emulation in QEMU
  ☆89Updated 2 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆107Updated 4 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆127Updated last week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆184Updated 8 months ago