Alternatives and similar repositories for c3-simulator:

Users that are interested in c3-simulator are comparing it to the libraries listed below

• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆23Updated last year
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆12Updated last month
• intel / pfr-wilson-city
  ☆24Updated 6 months ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 5 months ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆24Updated 6 months ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆35Updated 2 years ago
• antmicro / rowhammer-tester
  ☆60Updated 2 months ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• NetTLP / libtlp
  A library for PCIe Transaction Layer
  ☆56Updated 2 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆32Updated 3 years ago
• proteus-core / prospect
  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
  ☆16Updated last week
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆37Updated 2 weeks ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆52Updated last week
• CTSRD-CHERI / cheri-specification
  CHERI ISA Specification
  ☆24Updated 9 months ago
• RSPwFPGAs / virtio-fpga
  A platform for emulating Virtio devices with FPGAs
  ☆25Updated 4 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated last month
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆11Updated 3 weeks ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆16Updated last month
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆61Updated 5 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 6 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• ics-jku / spinalfuzz
  Fuzzing for SpinalHDL
  ☆16Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago