genieacs / espresso-iisojs
Implementation of Espresso-II method for heuristic minimization of single output boolean functions
☆28Updated 11 months ago
Alternatives and similar repositories for espresso-iisojs:
Users that are interested in espresso-iisojs are comparing it to the libraries listed below
- Espresso heuristic logic minimizer made C++20 Windows 10 compatible - University of California, Berkeley☆47Updated 11 months ago
- The glucose SAT solver☆92Updated 3 months ago
- Qute: a dependency learning QBF solver.☆12Updated 2 months ago
- configurable, high-performance SAT solver, implementing incremental solving interface of MiniSat and IPASIR. Based on MiniSat (minisat.se…☆41Updated last year
- C++ truth table library☆51Updated 10 months ago
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆45Updated last week
- The HW-CBMC and EBMC Model Checkers for Verilog☆65Updated this week
- Multi-core Decision Diagram (BDD/LDD) implementation☆42Updated last year
- A hardware model checker for hyperproperties☆18Updated 8 months ago
- An advanced header-only exact synthesis library☆24Updated 2 years ago
- A circuit toolkit☆97Updated 4 years ago
- This repository contains the code of Intel(R) SAT Solver (IntelSAT)☆27Updated this week
- ☆11Updated 7 years ago
- Benchmarking Suite for BDD packages☆14Updated 2 months ago
- A fast and certifying solver for quantified Boolean formulas.☆26Updated 9 months ago
- CoreIR Symbolic Analyzer☆64Updated 4 years ago
- ☆13Updated 4 years ago
- Random Generator of Btor2 Files☆9Updated last year
- BTOR2 MLIR project☆23Updated last year
- CNF minimizer and minimal independent set calculator☆18Updated 7 months ago
- Cube-and-Conquer SAT solver☆32Updated last year
- Hardware Model Checker☆32Updated this week
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- SAT Heritage: a community-driven effort for archiving, building and running more than thousand SAT solvers☆38Updated 2 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆18Updated last month
- ☆27Updated 9 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 7 months ago
- ☆34Updated 7 months ago
- ☆15Updated 11 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago