Alternatives and similar repositories for espresso-iisojs

Users that are interested in espresso-iisojs are comparing it to the libraries listed below

• Gigantua / Espresso
  Espresso heuristic logic minimizer made C++20 Windows 10 compatible - University of California, Berkeley
  ☆50Updated last year
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆73Updated last week
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆145Updated 5 years ago
• TheProjecter / eqntott
  Automatically exported from code.google.com/p/eqntott
  ☆14Updated 9 years ago
• lsils / kitty
  C++ truth table library
  ☆56Updated 2 weeks ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆22Updated 3 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆72Updated this week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated this week
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆13Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆43Updated last month
• MaartenBaert / xormix
  A hardware-optimized high-quality pseudorandom number generator
  ☆36Updated last year
• msoeken / cirkit
  A circuit toolkit
  ☆102Updated 5 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆103Updated last week
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆78Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• utwente-fmt / sylvan
  Multi-core Decision Diagram (BDD/LDD) implementation
  ☆44Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆142Updated last week
• alexander-nadel / intel_sat_solver
  This repository contains the code of Intel(R) SAT Solver (IntelSAT)
  ☆29Updated 2 months ago
• martinjonas / Q3B
  ☆28Updated 2 months ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• scottinet / espresso-logic-minimizer
  A Node.js bridge to the Espresso heuristic logic minimizer original C code
  ☆40Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆98Updated 3 months ago
• eytans / easter-egg
  easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once
  ☆13Updated 2 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆92Updated 11 months ago
• cucapra / patronus
  work in progress, playing around with btor2 in rust
  ☆11Updated 2 weeks ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆23Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆87Updated last week