Verik toolchain
☆47Dec 24, 2022Updated 3 years ago
Alternatives and similar repositories for verik
Users that are interested in verik are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Mar 3, 2026Updated 4 months ago
- Simple RISC-V processor for FPGAs☆21Apr 18, 2023Updated 3 years ago
- Various tools written or modified by me☆10Apr 14, 2026Updated 3 months ago
- A Simple Abstract Interpreter, built for teaching purposes☆21May 13, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆17Jun 5, 2024Updated 2 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated 2 years ago
- C version of PERSHING, a place-and-route tool for Minecraft Redstone circuits☆23Apr 8, 2018Updated 8 years ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- GDSII manipulation library☆17Dec 13, 2025Updated 7 months ago
- D3.js based wave (signal) visualizer☆68Jun 9, 2026Updated last month
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- ☆21Updated this week
- Filelist generator☆21Jun 23, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆14Aug 12, 2020Updated 5 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework☆97Updated this week
- JSON lib in Systemverilog☆44Feb 23, 2022Updated 4 years ago
- OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation☆14Jun 18, 2026Updated last month
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 8 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆36Dec 11, 2025Updated 7 months ago
- Interchange formats for chip design.☆39Feb 15, 2026Updated 5 months ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆12Nov 8, 2020Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆53Jul 21, 2022Updated 4 years ago
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languag…☆489Updated this week
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 3 years ago
- egraphs-good website☆18Mar 10, 2026Updated 4 months ago
- Evaluate mathematical expressions in selection regions inline (deprecated)☆21Aug 28, 2017Updated 8 years ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 11 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An IntelliJ-based IDE plugin for Python AST transformations☆19Aug 16, 2023Updated 2 years ago
- Replace Tcl scripting with Python☆18Apr 3, 2026Updated 3 months ago
- Examples of using Diderot☆10Sep 16, 2019Updated 6 years ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆259Updated this week
- A simple demo that shows how WebWorkers can be used in Kotlin/JS☆10May 21, 2021Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆469Updated this week
- Multiplatform dynamic visualization framework including Plotly-kt☆44Jul 18, 2026Updated last week