Alternatives and similar repositories for verik

Users that are interested in verik are comparing it to the libraries listed below

• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆104Updated 2 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last month
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆121Updated last week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated last month
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆184Updated last year
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 4 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆129Updated this week
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆109Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated 4 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆175Updated this week
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆92Updated this week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆49Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated this week
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆195Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆223Updated 10 months ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆101Updated this week
• antmicro / sv-bugpoint
  ☆34Updated last week
• schoeberl / wildcat
  An implementation of RISC-V
  ☆46Updated last month
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last month