frwang96 / verik
Verik toolchain
☆41Updated 2 years ago
Alternatives and similar repositories for verik:
Users that are interested in verik are comparing it to the libraries listed below
- The specification for the FIRRTL language☆51Updated this week
- ☆52Updated 2 years ago
- WAL enables programmable waveform analysis.☆142Updated last week
- A SystemVerilog source file pickler.☆54Updated 3 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆138Updated last week
- SystemVerilog frontend for Yosys☆69Updated last week
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆136Updated this week
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- RISC-V Formal Verification Framework☆123Updated last week
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆83Updated 10 months ago
- Generic Register Interface (contains various adapters)☆103Updated 4 months ago
- A command-line tool for displaying vcd waveforms.☆50Updated 11 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆165Updated 6 months ago
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆99Updated 7 months ago
- high-performance RTL simulator☆150Updated 7 months ago
- Raptor end-to-end FPGA Compiler and GUI☆73Updated last month
- RISC-V System on Chip Template☆156Updated this week
- Chisel/Firrtl execution engine☆153Updated 5 months ago
- 64-bit multicore Linux-capable RISC-V processor☆84Updated 4 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆85Updated this week
- SystemVerilog synthesis tool☆177Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 2 months ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆83Updated this week