Alternatives and similar repositories for verik

Users that are interested in verik are comparing it to the libraries listed below

• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆164Updated 3 months ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆124Updated this week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆106Updated this week
• Kuree / kratos
  Debuggable hardware generator
  ☆71Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆91Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆95Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆196Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆134Updated this week
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆78Updated 2 weeks ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆118Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• pieter3d / simview
  ☆91Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 7 months ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆49Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆155Updated last year
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆43Updated 3 weeks ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆47Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆227Updated 11 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago