frwang96 / verikLinks
Verik toolchain
☆44Updated 2 years ago
Alternatives and similar repositories for verik
Users that are interested in verik are comparing it to the libraries listed below
Sorting:
- WAL enables programmable waveform analysis.☆155Updated 2 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆82Updated last week
- ACT hardware description language and core tools.☆119Updated this week
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- A SystemVerilog source file pickler.☆59Updated 10 months ago
- FPGA tool performance profiling☆102Updated last year
- Structural Netlist API (and more) for EDA post synthesis flow development☆112Updated this week
- Hardware generator debugger☆75Updated last year
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week
- ☆56Updated 3 years ago
- Equivalence checking with Yosys☆45Updated 2 weeks ago
- RISC-V Formal Verification Framework☆145Updated last week
- A hardware compiler based on LLHD and CIRCT☆263Updated last month
- Logic circuit analysis and optimization☆43Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- SystemVerilog frontend for Yosys☆151Updated 2 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Open-source FPGA research and prototyping framework.☆209Updated last year
- The specification for the FIRRTL language☆63Updated last week
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- SystemVerilog synthesis tool☆208Updated 5 months ago
- high-performance RTL simulator☆173Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 11 months ago
- Mutation Cover with Yosys (MCY)☆86Updated 2 weeks ago
- Debuggable hardware generator☆69Updated 2 years ago
- An automatic clock gating utility☆50Updated 4 months ago
- FPGA Assembly (FASM) Parser and Generator☆95Updated 3 years ago
- ☆29Updated 2 weeks ago
- ☆79Updated last year