freecores / orsoc_graphics_accelerator
ORSoC Graphics Accelerator
☆9Updated 10 years ago
Related projects: ⓘ
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆15Updated 2 months ago
- IEEE 754 floating point library in system-verilog and vhdl☆26Updated 4 months ago
- A small 32-bit implementation of the RISC-V architecture☆31Updated 4 years ago
- MMC (and derivative standards) host controller☆22Updated 4 years ago
- SystemC to Verilog Synthesizable Subset Translator☆9Updated last year
- Ethernet MAC 10/100 Mbps☆24Updated 2 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆70Updated 12 years ago
- ☆10Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- PCI bridge☆14Updated 10 years ago
- Cortex-M0 DesignStart Wrapper☆17Updated 5 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆19Updated this week
- USB 2.0 FS Device controller IP core written in SystemVerilog☆32Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- USB Full Speed PHY☆38Updated 4 years ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- DSP WishBone Compatible Cores☆11Updated 10 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆17Updated 6 years ago
- Hamming ECC Encoder and Decoder to protect memories☆26Updated 3 months ago
- verilog/FPGA hardware description for very simple GPU☆16Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆19Updated 6 years ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆20Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆16Updated 10 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- USB -> AXI Debug Bridge☆33Updated 3 years ago
- Wishbone interconnect utilities☆34Updated 3 months ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated last month
- turbo 8051☆28Updated 7 years ago
- Embedded 32-bit RISC uProcessor with SDRAM Controller☆24Updated 3 years ago
- Bluespec H.264 Decoder☆11Updated 10 years ago