Alternatives and similar repositories for orsoc_graphics_accelerator

Users that are interested in orsoc_graphics_accelerator are comparing it to the libraries listed below

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• srimanthtenneti / SOC-Design-ARM-M0
  This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
  ☆11Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 5 months ago
• RoaLogic / vga_lcd
  VGA LCD Core (OpenCores)
  ☆14Updated 7 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆26Updated last week
• freecores / bluespec-h264
  Bluespec H.264 Decoder
  ☆11Updated 10 years ago
• freecores / theia_gpu
  Theia: ray graphic processing unit
  ☆20Updated 10 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• Wren6991 / HyperRam
  simple hyperram controller
  ☆11Updated 6 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆44Updated 5 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 10 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 4 months ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• freecores / sgmii
  SGMII
  ☆12Updated 10 years ago
• voldemoriarty / Matmul
  Matrix Multiplication in Hardware
  ☆16Updated 5 years ago
• maidenone / ORGFXSoC
  An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
  ☆72Updated 13 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆29Updated 12 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• jeras / rp32
  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
  ☆15Updated 2 weeks ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• freecores / wb_builder
  WISHBONE Builder
  ☆14Updated 8 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago