Alternatives and similar repositories for netlist-viewer

Users that are interested in netlist-viewer are comparing it to the libraries listed below

• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆36Updated 5 years ago
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆23Updated 4 years ago
• Qucs / qucsator
  Circuit simulator of the Qucs project
  ☆29Updated 4 months ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆41Updated 10 months ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆52Updated 2 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆116Updated last month
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆78Updated last month
• dwarning / VA-Models
  Verilog-A simulation models
  ☆71Updated 4 months ago
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆100Updated 2 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆65Updated this week
• idea-fasoc / fasoc
  ☆54Updated last year
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆47Updated last month
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 3 years ago
• snishizawa / libretto
  Characterizer
  ☆22Updated last week
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆28Updated 2 weeks ago
• mineda-support / ICPS2023_5
  ☆52Updated 2 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆100Updated this week
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆47Updated 3 months ago
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆33Updated 2 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆62Updated last week
• efabless / mpw_precheck
  ☆39Updated 2 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆28Updated 2 weeks ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆78Updated 4 months ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆40Updated 2 months ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated last week
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆55Updated last year