Alternatives and similar repositories for netlist-viewer

Users that are interested in netlist-viewer are comparing it to the libraries listed below

• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆128Updated last week
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 2 months ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆50Updated 5 months ago
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆60Updated this week
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆103Updated 3 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆78Updated 2 weeks ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆64Updated 5 months ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆39Updated 4 years ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆39Updated 5 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 3 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆88Updated 2 weeks ago
• Qucs / gnucsator
  This package provides a gnucap based qucsator implementation.
  ☆15Updated last week
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆13Updated this week
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆24Updated 5 years ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆41Updated last week
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆52Updated last year
• Xyce / XDM
  This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
  ☆22Updated last year
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆134Updated this week
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆42Updated 2 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆65Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆33Updated last month
• chipfoundry / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆75Updated 2 months ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆89Updated last year
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆69Updated 2 months ago
• siliconcompiler / scgallery
  SiliconCompiler Design Gallery
  ☆59Updated last week
• parallaxsw / OpenSTA
  ☆98Updated last week
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆34Updated 4 years ago
• mabrains / caravel_user_project_ldo
  Completed LDO Design for Skywaters 130nm
  ☆19Updated 2 years ago
• efabless / foss-asic-tools
  FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…
  ☆107Updated last year