foss-for-synopsys-dwc-arc-processors / openocd
The development tree for OpenOCD for the Synopsys DesignWare ARC processor family
☆14Updated last year
Alternatives and similar repositories for openocd:
Users that are interested in openocd are comparing it to the libraries listed below
- Ultimate ECP5 development board☆105Updated 5 years ago
- Project X-Ray Database: XC7 Series☆66Updated 3 years ago
- JTAG Tools For FTDI MPSSE Transports☆12Updated 10 years ago
- Repository containing releases of prebuilt GNU toolchains for DesignWare ARC Processors from Synopsys (available from "releases" link bel…☆96Updated last month
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 5 months ago
- Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.☆16Updated 8 years ago
- Documenting the Anlogic FPGA bit-stream format.☆86Updated 2 years ago
- JTAG boundary scan debug & test tool.☆144Updated 5 months ago
- Small footprint and configurable SATA core☆140Updated this week
- open-source logic analyzer for FPGAs☆96Updated 6 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆90Updated 5 years ago
- JTAG reverse engineering software for FTDI compatible cables☆51Updated 10 years ago
- Tools and Examples for IcoBoard☆80Updated 3 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 6 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- Small footprint and configurable JESD204B core☆42Updated 3 months ago
- Open source firmware for MMC controllers☆39Updated 2 weeks ago
- usb-jtag - Altera USB Blaster Emulation with a FX2☆70Updated 3 years ago
- MDX — A BSD-style RTOS☆26Updated 3 weeks ago
- FPGA USB stack written in LiteX☆126Updated 2 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Universal JTAG/SWD/UART adapter based on FT2232H☆29Updated 3 years ago
- UEFI, on Loongson.☆14Updated 8 years ago
- LatticeMico32 soft processor☆105Updated 10 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆53Updated 2 years ago
- Coresight Wire Protocol (CSWP) Server/Client and streaming trace examples.☆26Updated last month
- memtool is a program that allows to access memory mapped registers.☆27Updated 2 years ago