Alternatives and similar repositories for telebench:

Users that are interested in telebench are comparing it to the libraries listed below

• AlSaqr-platform / he-soc
  ☆31Updated this week
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆21Updated 4 years ago
• Minres / DBT-RISE-RISCV
  An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
  ☆35Updated this week
• RISCV-on-Microsemi-FPGA / CPUs
  CPUs
  ☆14Updated 4 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆48Updated 8 months ago
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated last month
• Vitorian / awesome-mpsoc
  Public resources available for Xilinx MPSOC+ and SDSOC hardware
  ☆18Updated 7 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆45Updated last month
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆55Updated 4 years ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 4 months ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆32Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• pavel-a / devmemX
  Program to read/write from/to any location in physical memory (cloned from devmem or devmem2). See wiki.
  ☆18Updated 5 years ago
• wsong83 / Asynchronous-Verilog-Synthesiser
  Synthesiser for Asynchronous Verilog Language
  ☆19Updated 10 years ago
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆23Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆90Updated this week
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆89Updated 5 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆54Updated 3 months ago
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆78Updated 3 years ago
• embecosm / embecosm-toolchain-releases
  ☆16Updated last week
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆27Updated 6 months ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year