Alternatives and similar repositories for meta-polarfire-soc-yocto-bsp

Users that are interested in meta-polarfire-soc-yocto-bsp are comparing it to the libraries listed below

• polarfire-soc / polarfire-soc-documentation
  PolarFire SoC Documentation
  ☆56Updated 2 months ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆45Updated 3 weeks ago
• devicetree-org / lopper
  ☆44Updated this week
• sifiveinc / meta-sifive
  SiFive OpenEmbedded / Yocto BSP Layer
  ☆53Updated last month
• Xilinx / yocto-manifests
  Repo Manifests for the Yocto Project Build System
  ☆32Updated last month
• polarfire-soc / polarfire-soc-linux-examples
  ☆16Updated 3 months ago
• polarfire-soc / polarfire-soc-bare-metal-examples
  Bare metal example software projects for PolarFire SoC
  ☆34Updated 4 months ago
• Xilinx / meta-xilinx-tools
  Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.
  ☆63Updated last month
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆68Updated 2 years ago
• polarfire-soc / icicle-kit-reference-design
  PolarFire SoC Icicle Kit Libero reference design
  ☆39Updated 3 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last week
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆104Updated 7 years ago
• beagleboard / beaglev-starlight
  ☆81Updated 3 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆61Updated 3 months ago
• Xilinx / bootgen
  bootgen source code
  ☆46Updated last month
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 4 months ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆65Updated 5 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 3 months ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆19Updated last month
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆76Updated 6 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆42Updated 2 weeks ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• nathanrossi / meta-hdl
  HDL tools layer for OpenEmbedded
  ☆17Updated 8 months ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 6 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆14Updated last month