csantosb / vhdl-toolsLinks
Easier navigation of VHDL sources
☆12Updated 5 years ago
Alternatives and similar repositories for vhdl-tools
Users that are interested in vhdl-tools are comparing it to the libraries listed below
Sorting:
- Verilog Extensions for Emacs☆61Updated last week
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆277Updated 3 weeks ago
- Tools for SystemVerilog development.☆15Updated 7 years ago
- A simple Emacs minor mode for VUnit☆12Updated 4 months ago
- A package for Sublime Text that aids coding in the VHDL language.☆42Updated 2 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- A JSON library implemented in VHDL.☆79Updated 3 years ago
- Streaming based VHDL parser.☆84Updated last year
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 8 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- ☆113Updated 4 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated 3 months ago
- FuseSoc Verification Automation☆22Updated 3 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)☆60Updated 4 years ago
- VHDL related news.☆27Updated this week
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- Useful set of library functions for VHDL☆47Updated 12 years ago
- FuseSoC standard core library☆149Updated 6 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 10 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 6 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- Advanced Encryption Standard (AES) SystemVerilog Core☆35Updated 7 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago