Alternatives and similar repositories for vim-hdl

Users that are interested in vim-hdl are comparing it to the libraries listed below

• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆221Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• wavedrom / cli
  CLI for WaveDrom
  ☆66Updated last year
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆41Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆32Updated 6 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆201Updated 3 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆74Updated last year
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆130Updated last year
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• Digilent / digilent-vivado-scripts
  ☆70Updated 6 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆112Updated 2 years ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• nachumk / systemverilog.vim
  SystemVerilog vim scripts
  ☆70Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆286Updated 6 years ago
• rubund / graywolf
  ☆114Updated 5 years ago
• imc-trading / svlangserver
  ☆129Updated 2 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆30Updated last year
• olofk / ipyxact
  Python-based IP-XACT parser and utilities
  ☆143Updated last year
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆82Updated last month
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 8 months ago
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆413Updated last year
• ZipCPU / vgasim
  A Video display simulator
  ☆175Updated 8 months ago
• sveditor / sveditor
  SystemVerilog Development Environment
  ☆54Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago