suoto / vim-hdl
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
☆60Updated 3 years ago
Alternatives and similar repositories for vim-hdl:
Users that are interested in vim-hdl are comparing it to the libraries listed below
- Repurposing existing HDL tools to help writing better code☆198Updated 7 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆94Updated 2 years ago
- FuseSoC standard core library☆125Updated 3 weeks ago
- SystemVerilog grammar for tree-sitter☆95Updated 2 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆78Updated 4 years ago
- Experimental flows using nextpnr for Xilinx devices☆221Updated 3 months ago
- A utility for Composing FPGA designs from Peripherals☆170Updated 3 weeks ago
- CLI for WaveDrom☆61Updated 10 months ago
- ☆76Updated 10 months ago
- Language server based on ghdl☆90Updated last year
- Regression test suite for Icarus Verilog. (OBSOLETE)☆116Updated last year
- Python tools for Vivado Projects☆73Updated 5 years ago
- SystemVerilog vim scripts☆65Updated last year
- ☆104Updated 7 months ago
- Verilog wishbone components☆113Updated last year
- Python package for writing Value Change Dump (VCD) files.☆110Updated 2 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆276Updated last week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆274Updated 5 years ago
- An Open Source configuration of the Arty platform☆124Updated last year
- Altera Advanced Synthesis Cookbook 11.0☆96Updated last year
- ☆64Updated 6 months ago
- Verilog/SystemVerilog Syntax and Omni-completion☆373Updated 3 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- A Video display simulator☆159Updated 6 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆116Updated 8 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆205Updated 2 months ago
- VCD file (Value Change Dump) command line viewer☆113Updated 2 years ago
- HDL symbol generator☆186Updated last year