suoto / vim-hdlLinks
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
☆60Updated 4 years ago
Alternatives and similar repositories for vim-hdl
Users that are interested in vim-hdl are comparing it to the libraries listed below
Sorting:
- Repurposing existing HDL tools to help writing better code☆218Updated last year
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- SystemVerilog grammar for tree-sitter☆113Updated last year
- Simple parser for extracting VHDL documentation☆72Updated last year
- Doxygen with verilog support☆40Updated 6 years ago
- Language server based on ghdl☆102Updated 7 months ago
- HDL symbol generator☆197Updated 2 years ago
- ☆88Updated 2 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆83Updated 5 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆283Updated 6 years ago
- SystemVerilog syntax highlight/indent support in vim☆51Updated last year
- FuseSoC standard core library☆150Updated this week
- Verilog wishbone components☆124Updated last year
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Python tools for Vivado Projects☆72Updated 6 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 9 months ago
- FPGA and Digital ASIC Build System☆80Updated 3 weeks ago
- ☆126Updated 3 weeks ago
- ☆114Updated 4 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Updated last year
- Python-based IP-XACT parser☆142Updated last year
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆117Updated 2 months ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Streaming based VHDL parser.☆84Updated last year
- CLI for WaveDrom☆63Updated last year
- SystemRDL 2.0 language compiler front-end☆268Updated 2 weeks ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- A JSON library implemented in VHDL.☆80Updated 3 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year