suoto / vim-hdlLinks
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
☆60Updated 4 years ago
Alternatives and similar repositories for vim-hdl
Users that are interested in vim-hdl are comparing it to the libraries listed below
Sorting:
- Repurposing existing HDL tools to help writing better code☆221Updated last year
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- Doxygen with verilog support☆41Updated 6 years ago
- SystemVerilog grammar for tree-sitter☆113Updated last year
- Language server based on ghdl☆102Updated 8 months ago
- ☆91Updated 3 months ago
- Simple parser for extracting VHDL documentation☆74Updated last year
- HDL symbol generator☆201Updated 3 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated 5 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆83Updated 6 years ago
- ☆114Updated 5 years ago
- FuseSoC standard core library☆151Updated 2 months ago
- Verilog wishbone components☆124Updated 2 years ago
- OSVVM Documentation☆36Updated last month
- Python tools for Vivado Projects☆72Updated 6 years ago
- VCD file (Value Change Dump) command line viewer☆120Updated 3 months ago
- CLI for WaveDrom☆66Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated last year
- FPGA and Digital ASIC Build System☆81Updated this week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆76Updated this week
- Python package for writing Value Change Dump (VCD) files.☆130Updated last year
- Playing around with Formal Verification of Verilog and VHDL☆65Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆91Updated this week
- A JSON library implemented in VHDL.☆82Updated last month
- ☆129Updated 2 months ago
- A command-line tool for displaying vcd waveforms.☆66Updated last year
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.☆42Updated 11 years ago