suoto / vim-hdl
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
☆60Updated 3 years ago
Alternatives and similar repositories for vim-hdl:
Users that are interested in vim-hdl are comparing it to the libraries listed below
- Repurposing existing HDL tools to help writing better code☆207Updated 11 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 2 years ago
- FuseSoC standard core library☆134Updated last month
- SystemVerilog vim scripts☆65Updated 2 years ago
- Python tools for Vivado Projects☆73Updated 6 years ago
- ☆78Updated last year
- Language server based on ghdl☆91Updated last month
- Doxygen with verilog support☆37Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- FPGA and Digital ASIC Build System☆74Updated this week
- ☆112Updated 4 years ago
- Altera Advanced Synthesis Cookbook 11.0☆103Updated 2 years ago
- Extensible FPGA control platform☆60Updated 2 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- A utility for Composing FPGA designs from Peripherals☆178Updated 4 months ago
- ☆38Updated last year
- CLI for WaveDrom☆62Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆80Updated 5 years ago
- Python package for writing Value Change Dump (VCD) files.☆117Updated 5 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- gdb python scripts for SystemC design introspection and tracing☆33Updated 6 years ago
- SystemVerilog grammar for tree-sitter☆99Updated 5 months ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- SystemVerilog syntax highlight/indent support in vim☆50Updated 9 months ago
- ☆69Updated last month
- Connectal is a framework for software-driven hardware development.☆168Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 8 months ago