A package for Sublime Text that aids coding in the VHDL language.
☆42Aug 18, 2023Updated 2 years ago
Alternatives and similar repositories for VHDL-Mode
Users that are interested in VHDL-Mode are comparing it to the libraries listed below
Sorting:
- SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)☆11Jun 19, 2024Updated last year
- Modern VSCode VHDL Support☆33Apr 10, 2022Updated 3 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last month
- RISC-V by VectorBlox☆11Jul 19, 2017Updated 8 years ago
- SystemVerilog Logger☆19Sep 30, 2025Updated 5 months ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Synthesizable FIR filters in VHDL☆14Jul 19, 2019Updated 6 years ago
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆22Oct 8, 2021Updated 4 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Dec 8, 2017Updated 8 years ago
- ☆25Apr 4, 2025Updated 11 months ago
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆23Oct 29, 2025Updated 4 months ago
- A macro system for YAML files powered by Python. Intended for Sublime Text development.☆22Oct 30, 2020Updated 5 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- VHDL formatter web online written in typescript☆58Jan 6, 2023Updated 3 years ago
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- synthesizable FFT IP block for FPGA designs☆32Apr 16, 2019Updated 6 years ago
- Style guide enforcement for VHDL☆234Feb 5, 2026Updated last month
- ☆33Apr 30, 2023Updated 2 years ago
- Simple parser for extracting VHDL documentation☆74Jul 12, 2024Updated last year
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 5 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆44Jan 18, 2024Updated 2 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- python串口示波器上位机☆11Dec 10, 2021Updated 4 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- tcl scripts used to build or generate vivado projects automatically☆34Jun 30, 2023Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆601Jul 30, 2025Updated 7 months ago
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Oct 5, 2020Updated 5 years ago
- cryptography ip-cores in vhdl / verilog☆41Feb 20, 2021Updated 5 years ago
- Open Component Portability Infrastructure☆62May 1, 2021Updated 4 years ago
- A Sublime Text 2 Plugin that can generate a sequence of numbers using search and replace.☆28Sep 29, 2019Updated 6 years ago
- Experimental Nix implementation of Android `soong` modules☆10Oct 11, 2023Updated 2 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- A DDS core written in VHDL.☆11Jan 5, 2019Updated 7 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago