Alternatives and similar repositories for VHDL-Mode

Users that are interested in VHDL-Mode are comparing it to the libraries listed below

• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆213Updated 3 weeks ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆188Updated 2 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆193Updated 2 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆245Updated last week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆56Updated 2 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆175Updated last month
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated last month
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 3 months ago
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆279Updated 5 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago
• TheClams / SystemVerilog
  SystemVerilog plugin for Sublime Text
  ☆48Updated last week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆76Updated last month
• themperek / cocotb-test
  Unit testing for cocotb
  ☆161Updated 2 months ago
• svunit / svunit
  ☆206Updated 5 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆61Updated 4 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆393Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆121Updated 2 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 7 months ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆222Updated 2 weeks ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆585Updated 2 weeks ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆134Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆142Updated this week