Alternatives and similar repositories for VHDL-Mode

Users that are interested in VHDL-Mode are comparing it to the libraries listed below

• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆225Updated last week
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆189Updated 2 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆195Updated 2 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆162Updated last month
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆249Updated 2 weeks ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆183Updated last month
• svunit / svunit
  ☆208Updated 7 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated 2 weeks ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 4 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆282Updated 5 years ago
• TheClams / SystemVerilog
  SystemVerilog plugin for Sublime Text
  ☆49Updated 3 weeks ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆149Updated last week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆56Updated 3 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated this week
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 8 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆62Updated 4 years ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆233Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆403Updated this week
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 10 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆409Updated 2 weeks ago
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆238Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆293Updated 2 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆68Updated this week
• rggen / rggen
  Code generation tool for control and status registers
  ☆427Updated last month