Alternatives and similar repositories for VHDL-Mode

Users that are interested in VHDL-Mode are comparing it to the libraries listed below

• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆211Updated last week
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆187Updated 2 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆191Updated 2 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆243Updated 3 weeks ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆172Updated this week
• svunit / svunit
  ☆204Updated 4 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 6 months ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆160Updated last month
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆133Updated last year
• wavedrom / cli
  CLI for WaveDrom
  ☆62Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• TheClams / SystemVerilog
  SystemVerilog plugin for Sublime Text
  ☆47Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆55Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆60Updated 4 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 5 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• raysalemi / Python4RTLVerification
  ☆161Updated 2 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated 8 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆277Updated 5 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆118Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆69Updated this week