An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
☆51Nov 23, 2013Updated 12 years ago
Alternatives and similar repositories for LVDS-7-to-1-Serializer
Users that are interested in LVDS-7-to-1-Serializer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DVI to LVDS Verilog converter☆25Sep 3, 2016Updated 9 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆64Oct 20, 2022Updated 3 years ago
- Basic code that displays simple shapes generated from Lattice FPGA directly to LVDS display☆29Jun 16, 2015Updated 10 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32May 15, 2023Updated 2 years ago
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆27May 3, 2020Updated 6 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 10 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- "The Drop" ASIC 640x480 60Hz audio visual demo☆14Feb 11, 2026Updated 2 months ago
- DC-SCM LTPI Reference Implementation☆21Jan 13, 2026Updated 3 months ago
- I2C ROM for EDID (Extended Display Identification Data) on FPGAs☆24Nov 13, 2015Updated 10 years ago
- Minimig project example for FleaFPGA Ohm Experimenter Board☆27May 17, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- AMIV☆18May 24, 2016Updated 9 years ago
- Miniature 8GHz FMCW Radar☆12Mar 29, 2016Updated 10 years ago
- Learn and build GPU RTL from scratch☆20Aug 1, 2025Updated 9 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- An HDL design for sending data over Ethernet☆49Sep 13, 2025Updated 7 months ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- Another world port ESP32 TTGO VGA32 v1.4☆13Sep 23, 2024Updated last year
- FPGA display controller with support for VGA, DVI, and HDMI.☆255Jan 28, 2026Updated 3 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- VHDL simulation model for PADAUK PDK microcontrollers☆21May 20, 2020Updated 5 years ago
- An embeddable FPGA SoM designed for high-speed audio and USB applications.☆27Mar 9, 2026Updated 2 months ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- Must-have verilog systemverilog modules☆38May 1, 2022Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 8 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆18Nov 16, 2023Updated 2 years ago
- ☆14Jul 12, 2016Updated 9 years ago
- Development Kit☆33Apr 23, 2019Updated 7 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated last month
- Sigma-Delta Analog to Digital Converter in FPGA (VHDL)☆15Dec 19, 2017Updated 8 years ago
- Bitstream relocation and manipulation tool.☆52Feb 20, 2026Updated 2 months ago
- configurable cordic core in verilog☆54Jul 17, 2014Updated 11 years ago
- FPGA implementation of the AnotherWorld CPU (equivalent to the original VM)☆16Apr 6, 2020Updated 6 years ago
- 使用FPGA制作机器人，并使用python建立上位机，FPGA机器人通过控制ESP8266通过WiFi进行无线通讯，来达到上位机控制FPGA机器人的目的☆27Jul 31, 2020Updated 5 years ago