Alternatives and similar repositories for CPU2006-Express

Users that are interested in CPU2006-Express are comparing it to the libraries listed below

• hanhwi / SimPoint
  ☆17Updated 3 years ago
• ucb-bar / ccbench
  Memory System Microbenchmarks
  ☆63Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• LvNA-system / labeled-RISC-V
  ☆168Updated 4 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• brucechin / HardwareTest
  hardware test for CPU，GPU，I/O，memory bandwidth performance
  ☆25Updated 6 years ago
• CMU-SAFARI / BEER
  BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…
  ☆19Updated 4 years ago
• shinezyy / gem5-official-old
  ☆20Updated 4 years ago
• ccelio / riscv-hpmcounters
  A simple utility for doing RISC-V HPM perf monitoring.
  ☆16Updated 8 years ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 8 years ago
• LvNA-system / PARD-gem5
  Full-system simulator for PARD architecture based on gem5
  ☆53Updated 10 years ago
• ArmDeveloperEcosystem / cmn-tools
  Performance and diagnostic tools for Arm CMN on-chip interconnects
  ☆15Updated last week
• vortexgpgpu / pocl
  a clone of POCL that includes RISC-V newlib devices support and Vortex
  ☆45Updated last week
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago
• tonyho / ARM_BenchMark
  A copy from of ARM Benchmark tools souce code: lmbench dhrystone fhourstones Linpack whetstone.
  ☆39Updated 11 years ago
• utcs-scea / ava
  Automatic virtualization of (general) accelerators.
  ☆43Updated 2 years ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated 2 months ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆34Updated 2 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆61Updated 2 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• foss-for-synopsys-dwc-arc-processors / lmbench
  LMBench for ARC - based off of tarball from sourceforge, slightly modified for post-processing ease
  ☆34Updated last year
• aakahlow / gem5Valid_Haswell
  ☆20Updated 5 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆26Updated 2 months ago
• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆41Updated 3 months ago
• sparcians / stf_spec
  An open-source Simulation Trace Format specification
  ☆15Updated last month
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆36Updated 7 years ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago