Alternatives and similar repositories for sanctum

Users that are interested in sanctum are comparing it to the libraries listed below

• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 7 months ago
• jasonyu1996 / elasticlave
  ☆23Updated 4 months ago
• riscv-admin / trusted-computing
  ☆22Updated 2 years ago
• Penglai-Enclave / Penglai-Enclave
  This is the main repo for Penglai.
  ☆70Updated last year
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 5 months ago
• pwnall / sanctum
  Minimal RISC Extensions for Isolated Execution
  ☆53Updated 6 years ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆58Updated 2 months ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• Penglai-Enclave / Penglai-Enclave-TVM
  The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).
  ☆40Updated 2 years ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated 6 months ago
• CactiLab / BYOTee-Build-Your-Own-TEEs
  ☆22Updated last year
• sam1013 / timberv-riscv-tools
  RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
  ☆21Updated 6 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated last month
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 4 months ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆119Updated last month
• Penglai-Enclave / Penglai-Enclave-sPMP
  Penglai Enclave is an open-sourced, secure and scalable TEE system for RISC-V.
  ☆142Updated 4 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• saiteja-talluri / Microarchitectural-attacks
  Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
  ☆10Updated 5 years ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆20Updated 3 weeks ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆86Updated last year
• Compass-All / SHELTER
  ☆34Updated 2 years ago
• compsec-snu / difuzz-rtl
  ☆90Updated last year
• michaeljclark / rv8-bench
  rv8 benchmark suite
  ☆20Updated 5 years ago
• nagnagnet / PrimeProbe
  ☆19Updated 6 years ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated last week
• sectrs-acai / acai
  Protecting Accelerator Execution with Arm Confidential Computing Architecture (USENIX Security 2024)
  ☆26Updated last year