Alternatives and similar repositories for sanctum

Users that are interested in sanctum are comparing it to the libraries listed below

• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 6 months ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 3 months ago
• Penglai-Enclave / Penglai-Enclave
  This is the main repo for Penglai.
  ☆69Updated last year
• pwnall / sanctum
  Minimal RISC Extensions for Isolated Execution
  ☆53Updated 6 years ago
• jasonyu1996 / elasticlave
  ☆23Updated 4 months ago
• riscv-admin / trusted-computing
  ☆22Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 2 weeks ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆57Updated last month
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated 6 months ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• proteus-core / prospect
  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
  ☆18Updated 2 weeks ago
• sam1013 / timberv-riscv-tools
  RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
  ☆21Updated 6 years ago
• michaeljclark / rv8-bench
  rv8 benchmark suite
  ☆20Updated 4 years ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆119Updated 3 weeks ago
• CactiLab / BYOTee-Build-Your-Own-TEEs
  ☆22Updated last year
• Penglai-Enclave / Penglai-Enclave-TVM
  The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).
  ☆39Updated 2 years ago
• sslab-gatech / SNAP
  ☆14Updated 3 years ago
• compsec-snu / difuzz-rtl
  ☆88Updated last year
• sectrs-acai / acai
  Protecting Accelerator Execution with Arm Confidential Computing Architecture (USENIX Security 2024)
  ☆26Updated last year
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆85Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• TwinVisor / twinvisor-prototype
  ☆23Updated 2 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated last week
• Penglai-Enclave / Penglai-Enclave-sPMP
  Penglai Enclave is an open-sourced, secure and scalable TEE system for RISC-V.
  ☆140Updated 4 months ago
• Miro-H / CacheSC
  Library for Prime+Probe cache side-channel attacks on L1 and L2
  ☆34Updated 5 years ago