Fibre Channel / FICON HBA implemented on FPGA
☆40May 9, 2021Updated 4 years ago
Alternatives and similar repositories for fejkon
Users that are interested in fejkon are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆66Feb 20, 2026Updated last month
- NeTV2 SoC based on LiteX☆17Jul 17, 2018Updated 7 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- SD device emulator from ProjectVault☆19Sep 24, 2019Updated 6 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- Quickstart for building FPGA code for NeTV2☆89Jul 13, 2023Updated 2 years ago
- Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)☆16Aug 16, 2021Updated 4 years ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated last year
- PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical…☆12Apr 29, 2023Updated 2 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 7 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- Multi Party Authorization version of sudo/doas☆20Sep 4, 2025Updated 6 months ago
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- ☆56Jul 22, 2022Updated 3 years ago
- PReP emulation on Power8☆32Nov 5, 2016Updated 9 years ago
- Better living through BSD☆18Oct 27, 2020Updated 5 years ago
- Python interface to PCIE☆40Apr 30, 2018Updated 7 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- Icarus SIMBUS☆20Nov 6, 2019Updated 6 years ago
- GCC port rewrite for OpenRISC☆12May 28, 2025Updated 9 months ago
- Verilog based simulation modell for 7 Series PLL☆17May 4, 2020Updated 5 years ago
- Protoboard cartridge for the Hackaday 2019 Supercon badge☆17Nov 12, 2019Updated 6 years ago
- A Z80 CPU implemented in Chisel.☆11Sep 20, 2020Updated 5 years ago
- Notes on/tools for/new firmware for (?) a PDC002 USB PD cable☆17Apr 8, 2021Updated 4 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- EasyNIC: an easy-to-use host interface for network cards☆43May 30, 2018Updated 7 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- SPI flash MITM and emulation (QSPI is a WIP)☆20Jan 27, 2022Updated 4 years ago
- Hoddarla is an OS project in Golang targeting RISC-V 64-bit system.☆12Oct 28, 2021Updated 4 years ago
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- standalone python host-side module to talk to OpenVizsla devices, based on LibOV [archived]☆18Feb 1, 2024Updated 2 years ago
- NJE (Network Job Entry) server and client implemented in C#☆11Jan 29, 2021Updated 5 years ago
- Parametric OpenSCAD model for making coil forms for coax-traps for wire antennas.☆17Jun 25, 2020Updated 5 years ago
- "L7" Policies for RabbitMQ, powered by BPF☆13Feb 25, 2021Updated 5 years ago
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆108Jun 23, 2018Updated 7 years ago
- ☆15May 11, 2025Updated 10 months ago