bluecmd / fejkon
Fibre Channel / FICON HBA implemented on FPGA
☆38Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for fejkon
- An FPGA/PCI Device Reference Platform☆28Updated 3 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆93Updated last year
- ☆39Updated 3 years ago
- A FPGA implementation of the NTP and NTS protocols☆51Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆86Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated 3 weeks ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development☆49Updated 2 months ago
- Open source FPGA-based NIC and platform for in-network compute☆58Updated 3 weeks ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆39Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆76Updated 4 years ago
- Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM☆36Updated 9 months ago
- A wishbone controlled scope for FPGA's☆73Updated 10 months ago
- LiteX development baseboards arround the SQRL Acorn.☆57Updated 7 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆61Updated 7 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆71Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆29Updated last year
- An open standard Cache Coherent Fabric Interface repository☆65Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- 妖刀夢渡☆56Updated 5 years ago
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆13Updated 3 years ago
- Small footprint and configurable SPI core☆39Updated 3 weeks ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- FuseSoC standard core library☆115Updated last month
- FPGA USB stack written in LiteX☆125Updated 2 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆52Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆36Updated 6 months ago
- Extensible FPGA control platform☆54Updated last year
- Portable HyperRAM controller☆48Updated last month
- Wishbone interconnect utilities☆37Updated 6 months ago