bluecmd / fejkonLinks
Fibre Channel / FICON HBA implemented on FPGA
☆39Updated 4 years ago
Alternatives and similar repositories for fejkon
Users that are interested in fejkon are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable SATA core☆154Updated last month
- ☆51Updated 4 years ago
- Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development☆70Updated 6 months ago
- An Open Source configuration of the Arty platform☆131Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆44Updated 4 years ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 7 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆51Updated 3 weeks ago
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆108Updated 7 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- An FPGA/PCI Device Reference Platform☆31Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- ☆53Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated this week
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- Use ECP5 JTAG port to interact with user design☆32Updated 4 years ago
- LiteX development baseboards arround the SQRL Acorn.☆72Updated 8 months ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 8 years ago
- VexRiscv-SMP integration test with LiteX.☆26Updated 5 years ago
- Experimental flows using nextpnr for Xilinx devices☆53Updated 3 weeks ago
- Small footprint and configurable SPI core☆46Updated this week
- Small footprint and configurable Ethernet core☆271Updated last month
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆70Updated 8 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- A wishbone controlled scope for FPGA's☆85Updated last year
- CMod-S6 SoC☆43Updated 7 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆57Updated 2 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆31Updated 3 years ago