32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.
☆15Aug 5, 2026Updated this week
Alternatives and similar repositories for Pipelined-RV32-SoC
Users that are interested in Pipelined-RV32-SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.☆23Aug 1, 2026Updated last week
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- ☆11Dec 8, 2018Updated 7 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 4 years ago
- Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators☆11Dec 26, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆22Jul 6, 2026Updated last month
- [NeurIPS 2024] BLAST: Block Level Adaptive Structured Matrix for Efficient Deep Neural Network Inference☆18Nov 6, 2024Updated last year
- ☆16May 21, 2026Updated 2 months ago
- 32-bit RISC-V based processor with memory controler☆16Sep 2, 2022Updated 3 years ago
- Deep-learning framework for MRI segmentation☆57Jul 13, 2026Updated 3 weeks ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆62Nov 23, 2021Updated 4 years ago
- ☆16Apr 7, 2026Updated 4 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆44Jan 15, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆20Nov 26, 2024Updated last year
- NTUST Calendar Maker | 台科大日 曆製作工具☆33Mar 12, 2025Updated last year
- Implementation of 5 Stage 32I RISC V Pipeline Processor.☆34Sep 6, 2024Updated last year
- ☆15Mar 22, 2024Updated 2 years ago
- Torch MinGRU implementation based on "Were RNNs All We Needed?"☆23Dec 5, 2024Updated last year
- This project will use ZYNQ 7020 to build the PYNQ framework, and build face detection algorithm, and finally use USB camera to detect fac…☆27Dec 17, 2021Updated 4 years ago
- This project describes how the cv2PYNQ python library was built☆21Aug 2, 2018Updated 8 years ago
- ☆33Jun 8, 2022Updated 4 years ago
- IC-contest 2012~2024☆25Apr 30, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 武汉大学计算机学院实验报告LaTeX模板☆51Jun 26, 2019Updated 7 years ago
- A C++ implementation of a 3 layer Gated Recurrent Unit (GRU) using no libraries other than Eigen for Matrices.☆23Jan 28, 2020Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆38Feb 21, 2018Updated 8 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- Built a convolutional neural network on the PYNQ-Z2 platform and accelerated traffic sign recognition using FPGA.☆30Jul 11, 2025Updated last year
- PyTorch implementation of "Dynamic Structure Pruning for Compressing CNNs" (AAAI 2023 Oral)☆28Jan 15, 2024Updated 2 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 3 months ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆71May 8, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆66Jul 5, 2024Updated 2 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- A toy x86 disassembler and x86 style toy chip☆15Dec 30, 2011Updated 14 years ago
- Neovim plugin for Python testing☆103Nov 12, 2025Updated 8 months ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆31Apr 7, 2025Updated last year
- C语言 矩阵的逆、矩阵乘法、矩阵行列式、矩阵转置/matrix inverse, matrix multiplication, matrix determination, matrix transpose☆10Dec 14, 2020Updated 5 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago