End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference
☆62Jul 29, 2026Updated 2 months ago
Alternatives and similar repositories for NPU-E2E
Users that are interested in NPU-E2E are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host i…☆20May 24, 2026Updated 4 months ago
- Open-source compiler that hardwires ternary BitNet weights into mask-programmed compute-in-ROM silicon on open PDKs☆47Sep 18, 2026Updated last month
- Python-first hardware construction toolkit with MLIR compilation, C++ simulation, and Verilog generation.☆40Updated this week
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- ☆29Mar 8, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- verilator testbench w/ Javascript using N-API☆18Feb 19, 2026Updated 8 months ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆24Nov 12, 2025Updated 11 months ago
- Extensions for the TG geometry library☆12Dec 3, 2024Updated last year
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆15Sep 9, 2022Updated 4 years ago
- ☆62Updated this week
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 5 years ago
- SGLang's TorchTPU Plugin☆24Updated this week
- learn llvm from scratch☆14Apr 29, 2023Updated 3 years ago
- 从零实现 LLM 推理引擎：15步学懂 vLLM 核心原理☆31Sep 9, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- CMSIS DSP Library for PULPino microcontroller☆24Aug 16, 2018Updated 8 years ago
- ☆14Mar 8, 2025Updated last year
- Verification IP for UART protocol☆26Aug 3, 2020Updated 6 years ago
- ☆31Aug 24, 2026Updated last month
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆23Updated this week
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆24Oct 25, 2024Updated last year
- Enemy UAV Detection with TensorFlow Lite Micro in LoRa mesh network☆13Nov 11, 2025Updated 11 months ago
- A Visual Studio Code symbols provider based on Ctags☆33Jun 30, 2026Updated 3 months ago
- MLIR-in as a compiler stack for ucb-bar☆21Oct 16, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆20Mar 18, 2022Updated 4 years ago
- Model, design, and explore tensor algebra accelerators.☆54Updated this week
- ICCD'24 paper: "AutoVCoder: A systematic framework for automated verilog code generation"☆27Dec 17, 2024Updated last year
- This is a tool to login qq zone using python, with multithreads to scrapy what you want,such as, message, blogs board, and photos.☆10May 11, 2017Updated 9 years ago
- 32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色，特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准（32 位）的浮点数加法器与除法…☆15Aug 14, 2025Updated last year
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- a simple plymouth replacement☆14Jan 25, 2016Updated 10 years ago
- SeekFree RT1064 Library GCC(VSCode) Porting☆12Oct 8, 2021Updated 5 years ago
- ☆25Aug 11, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- Language for simplifying parameterized RTL design☆13Apr 3, 2026Updated 6 months ago
- Adds more of the standard C/POSIX programming interface to Picolibc.☆15Feb 17, 2026Updated 8 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆57Sep 19, 2026Updated last month
- Open IP in Hardware Description Language.☆32Sep 4, 2023Updated 3 years ago
- A guide on how to fly ROS2-based multi-rotors manually and autonomously in Gazebo with PX4 in the loop☆14Mar 20, 2023Updated 3 years ago
- A GPU built from scratch which can render graphics and train ML models☆15Jul 4, 2026Updated 3 months ago