Repository for FPGA projects
☆78Jul 20, 2026Updated this week
Alternatives and similar repositories for RedPitaya-FPGA
Users that are interested in RedPitaya-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆24Apr 12, 2025Updated last year
- ☆53Jun 3, 2026Updated last month
- Collections of guides and projects related to testing RedPitaya☆59Nov 11, 2019Updated 6 years ago
- Simple projects for the RedPitaya board that illustrate the use of standard IPs from Vivado in combination with modules written in Verilo…☆18Aug 4, 2025Updated 11 months ago
- Transform the Red Pitaya in an acquisition card☆35Jun 15, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Notes on the Red Pitaya Open Source Instrument☆403Jul 7, 2026Updated 2 weeks ago
- Advanced DAQ Tools for the RedPitaya (STEMlab 125-14)☆45Jun 24, 2026Updated last month
- Lock-in and PID application for RedPitaya enviroment☆57Aug 21, 2025Updated 11 months ago
- SDK for FPGA / Linux Instruments☆111Jun 30, 2026Updated 3 weeks ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- Thesis: Custom Filter Designs on the Red Pitaya☆13Jan 8, 2018Updated 8 years ago
- Notes on the Eclypse Z7 development board☆17Apr 9, 2026Updated 3 months ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 4 months ago
- Spectroscopy lock application using RedPitaya☆127Jul 13, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆27Jun 26, 2014Updated 12 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- UART to AXI Stream interface written in VHDL☆19Oct 20, 2022Updated 3 years ago
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆25Apr 16, 2023Updated 3 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- Building your own SDR DDC/DUC transceiver with DIY modules from aliexpress☆33Nov 11, 2019Updated 6 years ago
- DSP by FPGA☆15Sep 12, 2023Updated 2 years ago
- The implementation of AD9371 on KC705☆21Jun 10, 2025Updated last year
- Python productivity for RFSoC platforms☆97Jul 3, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Software defined radio on a STM32H7 microcontroller☆15Sep 17, 2023Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode☆13Dec 9, 2018Updated 7 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- pyrpl turns your RedPitaya into a powerful DSP device, especially suitable as a lockbox in quantum optics experiments.☆202Updated this week
- AWGN signal generator IP for FPGA implemented by Verilog HDL with Fmax up to 320MHz on Xilinx Virtex Ultra-Scale FPGA.☆15Sep 20, 2020Updated 5 years ago
- FPGA Based lock in amplifier☆39Dec 28, 2023Updated 2 years ago
- RedPitaya application: Software Defined Radio (SDR) for an 8-channel WSPR receiver.☆10Jan 29, 2018Updated 8 years ago
- Forked from Beagle_SDR_GPS for specialized add-on SDR board with 16-Bit ADC which improved from KiwiSDR.☆15Sep 15, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Vector Network Analyzer 10 KHz - 180 MHz☆26Sep 2, 2018Updated 7 years ago
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 7 years ago
- A fresh Multichannel Analyser app for the Red Pitaya☆19Jul 5, 2024Updated 2 years ago
- Low-latency branching for heralded remote entanglement generation (ARTIQ).☆10Nov 22, 2023Updated 2 years ago
- PlutoSDR BSP build system based on buildroot☆10Sep 19, 2017Updated 8 years ago
- Tutorials available here:☆39Apr 7, 2026Updated 3 months ago
- Get ALL of the AKER Kit source file packs. If you love them, don't forget to tell us about it - aaron@akerkits.com☆10May 24, 2017Updated 9 years ago