altera-opensource / ghrd-socfpgaLinks
☆33Updated 9 months ago
Alternatives and similar repositories for ghrd-socfpga
Users that are interested in ghrd-socfpga are comparing it to the libraries listed below
Sorting:
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated last week
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 4 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 3 weeks ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- IEEE P1735 decryptor for VHDL☆39Updated 10 years ago
- Ethernet switch implementation written in Verilog☆55Updated 2 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- 国产VU13P加速卡资料☆81Updated 9 months ago
- ☆69Updated 5 months ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- ☆80Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- PCI Express controller model☆71Updated 3 years ago
- Ethernet interface modules for Cocotb☆72Updated 3 months ago
- ☆70Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- ☆28Updated 4 years ago
- ☆89Updated 8 years ago
- PCI express simulation framework for Cocotb☆185Updated 3 months ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- ☆36Updated 5 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated 2 months ago
- Verilog Ethernet Switch (layer 2)☆50Updated 2 years ago
- Verilog digital signal processing components☆162Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago