Alternatives and similar repositories for ghrd-socfpga

Users that are interested in ghrd-socfpga are comparing it to the libraries listed below

• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆55Updated this week
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 3 weeks ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆63Updated 7 months ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆38Updated last year
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• oprecomp / DDR4_controller
  ☆58Updated 4 years ago
• verilator / example-systemverilog
  ☆38Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆47Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆82Updated 5 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆57Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• antmicro / nvme-verilog-pcie
  ☆64Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆55Updated 3 weeks ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆163Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated 2 weeks ago
• aignacio / nox
  RISC-V Nox core
  ☆64Updated 2 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆121Updated 3 weeks ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 2 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 5 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆68Updated 9 months ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆41Updated 3 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago