altera-opensource / ghrd-socfpga

Related projects ⓘ

Alternatives and complementary repositories for ghrd-socfpga

• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆26Updated 9 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆47Updated 2 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆60Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆43Updated 11 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆47Updated this week
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆30Updated 10 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆22Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆46Updated 2 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆63Updated this week
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆56Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆57Updated 3 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆66Updated 3 weeks ago
• verilator / example-systemverilog
  ☆34Updated 10 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆58Updated 2 weeks ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual host model for verilog
  ☆84Updated last month
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆41Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆29Updated last year
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆36Updated 5 years ago