Alternatives and similar repositories for AES-GCM-128-192-256-bits

Users that are interested in AES-GCM-128-192-256-bits are comparing it to the libraries listed below

• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆25Updated last year
• Deepak42074 / Sky130-RTL-Design-And-Synthesis-Using-Verilog
  ☆15Updated 3 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆92Updated last year
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆77Updated 5 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆79Updated last week
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆66Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆119Updated this week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆70Updated this week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆67Updated 6 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last week
• verilator / example-systemverilog
  ☆40Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last month
• slaclab / axi-pcie-core
  ☆24Updated last week
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆49Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 9 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 10 months ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆49Updated 3 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated this week
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆115Updated this week
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆63Updated 4 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated last week