BLu85 / AES-GCM-128-192-256-bitsLinks
Configurable AES-GCM IP (128, 192, 256 bits)
☆38Updated 4 months ago
Alternatives and similar repositories for AES-GCM-128-192-256-bits
Users that are interested in AES-GCM-128-192-256-bits are comparing it to the libraries listed below
Sorting:
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆59Updated 3 weeks ago
- few python scripts to clone all IP cores from opencores.org☆25Updated last year
- A demo system for Ibex including debug support and some peripherals☆85Updated last month
- ☆21Updated 2 years ago
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- A reference book on System-on-Chip Design☆37Updated 6 months ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- HW Design Collateral for Caliptra RoT IP☆124Updated this week
- Playing around with Formal Verification of Verilog and VHDL☆64Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- Vivado build system☆69Updated 2 weeks ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆71Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- Control and Status Register map generator for HDL projects☆128Updated 7 months ago
- RISC-V Nox core☆71Updated 5 months ago
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 4 months ago
- ideas and eda software for vlsi design☆51Updated this week
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- Generate address space documentation HTML from compiled SystemRDL input☆59Updated last month