BLu85 / AES-GCM-128-192-256-bitsLinks
Configurable AES-GCM IP (128, 192, 256 bits)
☆39Updated 3 months ago
Alternatives and similar repositories for AES-GCM-128-192-256-bits
Users that are interested in AES-GCM-128-192-256-bits are comparing it to the libraries listed below
Sorting:
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- BlackParrot on Zynq☆47Updated 2 weeks ago
- ☆17Updated 3 years ago
- few python scripts to clone all IP cores from opencores.org☆25Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- Playing around with Formal Verification of Verilog and VHDL☆64Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆82Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- Mathematical Functions in Verilog☆95Updated 4 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆52Updated 4 months ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆19Updated 2 years ago
- RISC-V Nox core☆69Updated 4 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- An open-source HDL register code generator fast enough to run in real time.☆76Updated last week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated 2 months ago
- FPGA and Digital ASIC Build System☆80Updated 2 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆71Updated this week
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 3 years ago
- Vivado build system☆69Updated 3 weeks ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆70Updated 2 months ago
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆94Updated last year
- ☆26Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆73Updated 4 years ago