Production-ready, constant-time cryptographic keystream generators in pure Verilog. Fully hardened for ASIC/FPGA deployment, formally verified, and audited against side-channel leakage.
☆53Jul 18, 2026Updated 3 weeks ago
Alternatives and similar repositories for CipherCore
Users that are interested in CipherCore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A minimal neuromorphic chip design in SystemVerilog to learn how brain-inspired computing works from the ground up.☆29Mar 30, 2026Updated 4 months ago
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆19Apr 20, 2026Updated 3 months ago
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 4 months ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- VerilogAI – A specialized chatbot for Verilog. Supports code generation, debugging, and explanation with custom prompt engineering and AP…☆18Apr 26, 2026Updated 3 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 5 months ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated 2 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆31Mar 5, 2021Updated 5 years ago
- A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.☆23Aug 25, 2024Updated last year
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- This repo hold information on the open-standard OVP APIs☆20Dec 11, 2025Updated 7 months ago
- A novel Design-for-Test flow using LibreLane☆45May 9, 2026Updated 3 months ago
- Implementation of 5 Stage 32I RISC V Pipeline Processor.☆34Sep 6, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 6 months ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated last month
- ☆135Sep 2, 2023Updated 2 years ago
- Single Cycle 32 bit MIPS☆20Dec 24, 2022Updated 3 years ago
- HeiChips 2025 LibreLane Workshop☆16Aug 25, 2025Updated 11 months ago
- UART in Verilog and VHDL☆18Aug 21, 2022Updated 3 years ago
- ASIC implementation flow infrastructure, successor to OpenLane☆502Updated this week
- ☆17Jun 2, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Tiny Tapeout GDS Action (using LibreLane)☆25Jul 30, 2026Updated last week
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 9 years ago
- Single Instruction Multiple Threads GPU Core with textbook Streaming Multi-Processor features☆70Jan 30, 2026Updated 6 months ago
- An unnecessarily tiny and minimal implementation of GPT-2 in NumPy.☆11Feb 12, 2023Updated 3 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆21Jun 17, 2020Updated 6 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- ☆11Sep 23, 2022Updated 3 years ago
- 💾 FreeRTOS port for the NEORV32 RISC-V Processor.☆16Jul 27, 2026Updated 2 weeks ago
- Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm☆16May 28, 2015Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- ☆65Mar 31, 2025Updated last year
- ☆49Apr 7, 2024Updated 2 years ago
- ☆35May 25, 2026Updated 2 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆877Updated this week
- Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HD…☆32Updated this week
- An automated HDC platform☆11Mar 16, 2026Updated 4 months ago