deep learning library with pipeline for MNIST classification, synthesizable on DE1 SoC FPGAs
☆15Jan 15, 2025Updated last year
Alternatives and similar repositories for veri-nn
Users that are interested in veri-nn are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- minimal compiler☆24Feb 19, 2026Updated 7 months ago
- open-source assistant with computer use agents☆28Mar 6, 2026Updated 7 months ago
- a mini 2x2 systolic array and PE demo☆76Dec 21, 2025Updated 9 months ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 4 years ago
- XLSynth: Accelerated HW Synthesis☆18Oct 9, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- use Zybo z7-20☆17May 21, 2025Updated last year
- ☆10Dec 23, 2014Updated 11 years ago
- ☆175Jan 4, 2026Updated 9 months ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆15Aug 1, 2023Updated 3 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆14May 6, 2020Updated 6 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆24Aug 26, 2025Updated last year
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 7 years ago
- Here's all my Python/Numba (CUDA) code for the encoder block I made :)☆76Apr 28, 2025Updated last year
- Tandy 64 intro - for the Tandy 1000 HX☆10Mar 11, 2018Updated 8 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- ☆10Updated this week
- Transformer Architecture written with CUDA, C++ and LibTorch.☆11Jul 26, 2025Updated last year
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- In this repository I have simulated Memristors using Python3 and also created GUI for easy use by researchers to visualise the functionin…☆18Mar 30, 2019Updated 7 years ago
- Notes from learning RISC-V☆12Jun 30, 2026Updated 3 months ago
- 《CPU设计实战》学习记录及代码☆15Dec 30, 2023Updated 2 years ago
- Kikofri, a Jekyll Theme, and a fork of Kiko.☆17Jul 9, 2019Updated 7 years ago
- PYNQ DMA benchmark project☆12Apr 27, 2017Updated 9 years ago
- ☆29Apr 7, 2025Updated last year
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- Innovus backend scripts☆20Jun 20, 2022Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 本工程使用纯verilog编写rtl代码,在FPGA上搭建神经网络LeNet-5,实现手写数字识别的功能。☆42Nov 18, 2024Updated last year
- ☆14Updated this week
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆17Sep 18, 2026Updated last month
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头,使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后,在使用FAST计算图像特征点的同时,构建滑动窗口计算图像各个像素点的BRIEF描述符,完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配,最后…☆24Apr 16, 2025Updated last year
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- ☆20May 1, 2023Updated 3 years ago
- RTL and python for using the ADAU1761 audio codec on the Pynq-Z2 board from TUL☆13Dec 9, 2020Updated 5 years ago