☆246Oct 23, 2026Updated 2 weeks ago
Alternatives and similar repositories for ross-ai-assistant
Users that are interested in ross-ai-assistant are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WAR…☆172Updated this week
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆34Aug 14, 2026Updated 2 months ago
- An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram☆29Aug 10, 2026Updated 2 months ago
- ☆15Oct 7, 2026Updated last month
- MCP server that holds vivado and allows access to vivado without starting a new batch command every time☆69Feb 19, 2026Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Xilinx/AMD FPGA & MPSoC Vivado design skill for Claude — covers block design, IP config, XDC constraints, synthesis, implementation and b…☆482Apr 25, 2026Updated 6 months ago
- Python-first hardware construction toolkit with MLIR compilation, C++ simulation, and Verilog generation.☆44Updated this week
- AI-assisted FPGA development across AMD Vivado, Anlogic TangDynasty, and Intel Quartus.☆57Aug 17, 2026Updated 2 months ago
- Agent skill for Verilog-2001 RTL generation and FPGA design workflows.☆328Aug 25, 2026Updated 2 months ago
- ☆18Aug 17, 2026Updated 2 months ago
- Ref design combining the Zynq UltraScale+ MPSoC with the Hailo AI accelerator☆43Oct 26, 2026Updated last week
- FPGA hardware design guide based on real-world projects. Covers SystemVerilog, Vivado workflow, timing closure, CDC handling, and Xilin…☆20Feb 6, 2026Updated 9 months ago
- ☆19Dec 15, 2025Updated 10 months ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Agent skill for generating and verifying AGENTS.md files for coding agents.☆15Aug 26, 2026Updated 2 months ago
- ☆15Jun 8, 2026Updated 5 months ago
- Vitis In-Depth Tutorials☆1,628Sep 9, 2026Updated last month
- LLM-Aided FPGA Design and Debug Flow☆43Aug 1, 2025Updated last year
- XtraMAC code repo (Accepted by ISCA2026)☆32Sep 9, 2026Updated last month
- Open Logic FPGA Standard Library☆1,033Updated this week
- ☆15Jun 24, 2025Updated last year
- RFSoC QSFP Data Offload Design with GNU Radio☆33Jul 7, 2026Updated 4 months ago
- ☆19Apr 23, 2026Updated 6 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human er…☆18Mar 12, 2026Updated 7 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆43Sep 22, 2025Updated last year
- ☆29Jun 26, 2014Updated 12 years ago
- ☆825Jul 13, 2026Updated 3 months ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆37Jan 24, 2023Updated 3 years ago
- Vivado MCP Server — AI 驱动的 FPGA 开发助手，自动诊断 CRITICAL WARNING 并给出修复建议☆28Mar 12, 2026Updated 7 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆38Aug 12, 2026Updated 2 months ago
- AS02MC04 XCKU3P PCILeech-compatible FPGA port with 25G RawUDP transport on SFP1☆25Sep 17, 2026Updated last month
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Network Development Kit (NDK) for FPGA cards with example application☆99Updated this week
- A minimal, open-source Image Signal Processor (ISP) for AMD FPGA, implemented in Verilog.☆149Sep 26, 2026Updated last month
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆78Jun 2, 2024Updated 2 years ago
- TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs [FPGA2026]☆40Mar 11, 2026Updated 7 months ago
- Vitis Model Composer Examples and Tutorials☆130Oct 26, 2026Updated last week
- Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, wi…☆272Oct 23, 2026Updated 2 weeks ago
- Inference Engine for SiliconMind-V1 Verilog Coding Models☆54Jun 2, 2026Updated 5 months ago