Vivado MCP Server — AI 驱动的 FPGA 开发助手,自动诊断 CRITICAL WARNING 并给出修复建议
☆25Mar 12, 2026Updated 6 months ago
Alternatives and similar repositories for vivado-mcp
Users that are interested in vivado-mcp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Xilinx/AMD FPGA & MPSoC Vivado design skill for Claude — covers block design, IP config, XDC constraints, synthesis, implementation and b…☆436Apr 25, 2026Updated 4 months ago
- ☆173Sep 5, 2026Updated 2 weeks ago
- ☆47Aug 20, 2026Updated last month
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆28Aug 14, 2026Updated last month
- Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话,以及时序和 CRITICAL WAR…☆131Aug 9, 2026Updated last month
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆26Jul 30, 2025Updated last year
- ☆24May 3, 2026Updated 4 months ago
- AI-assisted FPGA development across AMD Vivado, Anlogic TangDynasty, and Intel Quartus.☆57Aug 17, 2026Updated last month
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 5 months ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- A toy x86 disassembler and x86 style toy chip☆15Dec 30, 2011Updated 14 years ago
- C语言 矩阵的逆、矩阵乘法、矩阵行列式、矩阵转置/matrix inverse, matrix multiplication, matrix determination, matrix transpose☆10Dec 14, 2020Updated 5 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 12 years ago
- Implementation of a RISC-V CPU in Verilog.☆19Jun 27, 2026Updated 2 months ago
- CUDA C simple application for Nvidia's GPU☆11Jun 7, 2022Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 12 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- ☆101Aug 25, 2025Updated last year
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- ☆11Dec 11, 2017Updated 8 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Aug 26, 2021Updated 5 years ago
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆13May 31, 2026Updated 3 months ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Agent skill for Verilog-2001 RTL generation and FPGA design workflows.☆291Aug 25, 2026Updated 3 weeks ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago