Alternatives and similar repositories for huaweicloud-fpga

Users that are interested in huaweicloud-fpga are comparing it to the libraries listed below

• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated last year
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆32Updated 6 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆71Updated last year
• huaweicloud / huaweicloud-fpga
  The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
  ☆53Updated 6 years ago
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆172Updated 5 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆341Updated this week
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆99Updated 2 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• bogdanvuk / pygears
  HW Design: A Functional Approach
  ☆146Updated 2 years ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆41Updated this week
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• riscv-boom / boom-template
  DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM
  ☆36Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆121Updated 2 years ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆49Updated 10 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆84Updated 4 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆275Updated 5 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• open-power / snap
  CAPI SNAP Framework Hardware and Software
  ☆110Updated 4 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆149Updated last year
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆73Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆130Updated 2 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆95Updated 2 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆57Updated 2 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆88Updated 8 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆82Updated 7 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆115Updated 4 years ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆91Updated 6 years ago