F35idk / spice-cpuLinks
An analog, transistor-level simulation of an 8-bit CPU in SPICE
☆12Updated 4 years ago
Alternatives and similar repositories for spice-cpu
Users that are interested in spice-cpu are comparing it to the libraries listed below
Sorting:
- This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board…☆12Updated 2 years ago
- Custom 6502 Video Game Console☆11Updated last year
- ☆12Updated 9 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆59Updated 2 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆16Updated 2 years ago
- ☆16Updated last year
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- RV32I single cycle simulation on open-source software Logisim.☆20Updated 2 years ago
- RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card☆40Updated last week
- A RISC-V CPU implementation☆14Updated 5 years ago
- Quite OK Image FPGA Encoder and Decoder☆21Updated 2 years ago
- Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K☆23Updated 3 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Updated 6 months ago
- FPGA Tetris written in Verilog☆13Updated 7 years ago
- ☆21Updated 8 years ago
- 16 bit RISC-V proof of concept☆24Updated last year
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆31Updated 2 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆101Updated 2 years ago
- Doom classic port to lightweight RISC‑V☆95Updated 3 years ago
- A small and simple rv32i core written in Verilog☆13Updated 3 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆32Updated 2 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC☆58Updated 2 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆39Updated 3 years ago
- RISC-V RV32E core designed for minimal area☆21Updated 10 months ago
- A very simple RISC-V ISA emulator.☆38Updated 4 years ago
- Programmable multichannel ADPCM decoder for FPGA☆24Updated 4 years ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆54Updated 2 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆45Updated last month