Alternatives and similar repositories for hello-world:

Users that are interested in hello-world are comparing it to the libraries listed below

• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆34Updated 3 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• kinap / AES-Processor
  AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…
  ☆15Updated 7 years ago
• ansonn / esl_systemc
  systemc建模相关
  ☆24Updated 10 years ago
• zhangly / azpr_cpu
  用Altera FPGA芯片自制CPU
  ☆39Updated 10 years ago
• huaweicloud / huaweicloud-fpga
  The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
  ☆50Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆72Updated 6 years ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆35Updated 5 years ago
• lingscale / cc01
  ☆31Updated last year
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆20Updated 8 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
  EE577b-Course-Project
  ☆15Updated 4 years ago
• CherrySprings / CherrySprings
  ☆17Updated last year
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆54Updated last year
• truecrab / VSCode_Extension_Verilog
  VSCode extension for enhancing verilog
  ☆24Updated 8 months ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• mballance / clusterv-soc
  Quad cluster of RISC-V cores with peripherals and local memory
  ☆23Updated 2 years ago
• sunyata000 / AMY_MCU
  A MCU implementation based PODES-M0O
  ☆18Updated 4 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆70Updated 3 years ago
• zhajio1988 / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆14Updated 7 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆10Updated last month
• FPGA-Networking / HyperParser
  ☆29Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• emwzq / example_uvm
  UVM实战随书源码
  ☆46Updated 5 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 7 years ago
• wangeddie67 / ESYSim
  ☆33Updated 7 months ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆100Updated 2 years ago
• MichaelMelkor / Vivado_Batch_Mode_Tool
  A tool for those who want to use Vivado's batch mode more easily
  ☆17Updated 5 years ago