Alternatives and similar repositories for bronzebeard:

Users that are interested in bronzebeard are comparing it to the libraries listed below

• theandrew168 / derzforth
  Bare-metal Forth implementation for RISC-V
  ☆47Updated 11 months ago
• zuloloxi / mecrisp-ice
  http://mecrisp.sourceforge.net/ Mecrisp-Ice is an enhanced version of Swapforth and the J1a stack processor by James Bowman, featuring th…
  ☆28Updated 8 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆28Updated 5 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆56Updated this week
• mcmenaminadrian / riscyforth
  Forth for RISC-V SBCs
  ☆30Updated last month
• microCore-VHDL / microCore
  Hardware/Software Co-design environment of a processor core for deterministic real time systems
  ☆37Updated last year
• aw / fiveforths
  32-bit RISC-V Forth for microcontrollers
  ☆74Updated 3 months ago
• samawati / j1eforth
  eForth for the j1 simulator and actual J1 FPGAs
  ☆34Updated 9 years ago
• technoblogy / ulisp-riscv
  A version of the Lisp programming language for RISC-V based boards.
  ☆28Updated 2 weeks ago
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆81Updated 6 months ago
• krakenlake / vmon
  RISC-V machine code monitor
  ☆33Updated last month
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year
• jamesbowman / j1
  The J1 CPU
  ☆164Updated 4 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆50Updated 4 years ago
• ThorKn / J1-forth
  Forth for the J1-CPU
  ☆17Updated 7 years ago
• enthusi / mandelbrot_riscv_assembler
  An example in bare metal RV32 assembly for the longan nano board
  ☆20Updated 3 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆83Updated 5 years ago
• Wren6991 / Hazard2
  Smol 2-stage RISC-V processor in nMigen
  ☆26Updated 3 years ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆15Updated 2 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆37Updated 4 years ago
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆21Updated 4 months ago
• zylin / zpugcc
  ☆51Updated 7 years ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆123Updated 4 months ago
• openXC7 / openXC7-snap
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆28Updated 6 months ago
• hutch31 / tv80
  TV80 Z80-compatible microprocessor
  ☆49Updated 4 years ago
• ulx3s / fpga-odysseus
  FPGA Odysseus with ULX3S
  ☆64Updated last year
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆48Updated 3 years ago
• mnemocron / my-discrete-fpga
  My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
  ☆41Updated 9 months ago
• ulx3s / ulx3s-toolchain
  ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts
  ☆39Updated 4 years ago